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    Physical partioning of logically continuous bus
    21.
    发明专利
    Physical partioning of logically continuous bus 未知

    公开(公告)号：SG42891A1

    公开(公告)日：1997-10-17

    申请号：SG1996000456

    申请日：1993-05-04

    Applicant: IBM

    Inventor： KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  SCHEIERN KEVIN LEE ,  VOORHEES RICHARD W ,  WACHTEL EDWARD IRVING

    IPC: G06F13/40 ,  G06F13/36

    Abstract: Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

    23.
    发明专利
    未知

    公开(公告)号：DE69026018D1

    公开(公告)日：1996-04-25

    申请号：DE69026018

    申请日：1990-09-11

    Applicant: IBM

    Inventor： KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  WACHTEL EDWARD IRVING

    IPC: G06F13/362 ,  G06F13/22 ,  G06F13/24 ,  G06F13/374

    Abstract: Apparatus and method for increasing efficiency of command execution from a host processor (11) over an SCSI bus (14). Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine (32). Additional protocol functions are implemented in a foreground state machine (26). When the host processor (11) issues a command for access to the SCSI bus (14), the background state machine (32) can be programmed before the foreground machine (26) completes the protocol function for a previous command. Thus, the background state machine (32) is ready to arbitrate for access to the bus (14) at the very next bus free condition.

    24.
    发明专利
    未知

    公开(公告)号：DE69024111D1

    公开(公告)日：1996-01-25

    申请号：DE69024111

    申请日：1990-06-11

    Applicant: IBM

    Inventor： DIXON JERRY DUANE ,  KEENER DON STEVEN ,  LOCKER HOWARD JEFFREY ,  MARAZAS GERALD ALLAN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN

    IPC: G06F13/14 ,  G06F12/06

    Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

    26.
    发明专利
    未知

    公开(公告)号：AT131640T

    公开(公告)日：1995-12-15

    申请号：AT90306343

    申请日：1990-06-11

    Applicant: IBM

    Inventor： DIXON JERRY DUANE ,  KEENER DON STEVEN ,  LOCKER HOWARD JEFFREY ,  MARAZAS GERALD ALLAN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN

    IPC: G06F13/14 ,  G06F12/06

    Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

    COMPUTER COMMAND INTERFACE
    27.
    发明专利
    COMPUTER COMMAND INTERFACE 未知

    公开(公告)号：NZ233824A

    公开(公告)日：1992-09-25

    申请号：NZ23382490

    申请日：1990-05-25

    Applicant: IBM

    Inventor： BONEVENTO FRANCIS MICHAEL ,  CHISHOLM DOUGLAS RODERICK ,  DODDS SAMMY DAVIS ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST NELSON ,  MCNEILL ANDREW BOYCE ,  MENDELSON RICHARD NEIL

    IPC: G06F13/12 ,  G06F13/00

    Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

    SUPPLEMENTARY PLATE WITH AUTOMATIC ADAPTATION TO GAP ATTACHMENT'S CONFIGURATION
    28.
    发明专利
    SUPPLEMENTARY PLATE WITH AUTOMATIC ADAPTATION TO GAP ATTACHMENT'S CONFIGURATION 未知

    公开(公告)号：CS9002917A2

    公开(公告)日：1991-11-12

    申请号：CS291790

    申请日：1990-06-12

    Applicant: IBM

    Inventor： MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN ,  REID EDDIE MILLER

    IPC: G06F3/00 ,  G06F13/40 ,  G06F15/00 ,  H01R9/00 ,  H01R29/00

    Abstract: A plug-in feature board (10) for a computer system has special circuitry to permit the board to customise itself to the particular slot into which it is inserted. Computers of the type intended for individual use or use in small networks typically provide insertion slots including connectors to permit feature boards to be added and connected to a bus of the computer for adding new function or capacity. As the computing power of such systems has increased there have been increases in the size of portions of the connecting bus to permit improvements in data transfer performance. In a given computer system there are often two or more bus connector (32) configurations presented in respective slots. By so converting electrical states at selected connector positions as to provide signal information for determining bus configuration for the slot, special logic provided on the board is enabled to determine the characteristics of the slot in which the board is placed and customises the board to respond or limit response in accordance with the requirements for that configuration. By so adapting to the slot the board achieves enhanced applicability and avoids certain system disabling malfunctions which can occur when a board is plugged into a slot for which it is not configured.

    EXTENSION CARD FOR COMPUTER WITH AUTOMATIC MATCHING CIRCUIT
    30.
    发明专利
    EXTENSION CARD FOR COMPUTER WITH AUTOMATIC MATCHING CIRCUIT 未知

    公开(公告)号：HU903801D0

    公开(公告)日：1990-11-28

    申请号：HU380190

    申请日：1990-06-11

    Applicant: IBM

    Inventor： MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN ,  REID EDDIE MILLER

    IPC: G06F3/00 ,  G06F13/40 ,  G06F15/00 ,  H01R9/00 ,  H01R29/00

    Abstract: A plug-in feature board (10) for a computer system has special circuitry to permit the board to customise itself to the particular slot into which it is inserted. Computers of the type intended for individual use or use in small networks typically provide insertion slots including connectors to permit feature boards to be added and connected to a bus of the computer for adding new function or capacity. As the computing power of such systems has increased there have been increases in the size of portions of the connecting bus to permit improvements in data transfer performance. In a given computer system there are often two or more bus connector (32) configurations presented in respective slots. By so converting electrical states at selected connector positions as to provide signal information for determining bus configuration for the slot, special logic provided on the board is enabled to determine the characteristics of the slot in which the board is placed and customises the board to respond or limit response in accordance with the requirements for that configuration. By so adapting to the slot the board achieves enhanced applicability and avoids certain system disabling malfunctions which can occur when a board is plugged into a slot for which it is not configured.

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