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    ASSOCIATIVE MEMORY AND DATA RETRIEVAL METHOD OF ASSOCIATIVE MEMORY
    22.
    发明专利
    ASSOCIATIVE MEMORY AND DATA RETRIEVAL METHOD OF ASSOCIATIVE MEMORY 失效

    公开(公告)号：JP2000149573A

    公开(公告)日：2000-05-30

    申请号：JP31300098

    申请日：1998-11-04

    Applicant: IBM

    Inventor： TANAKA MASAHIRO ,  MORI YOTARO ,  MIYATAKE HISATADA

    IPC: G11C15/04 ,  G11C15/00

    Abstract: PROBLEM TO BE SOLVED: To enable reduction of power consumption during the search operation by providing an identifying means to identify existence of data stored in a memory block and then retrieval only the memory block which as identified existence of data. SOLUTION: An associative memory is provided with a valid cell 10 for holding data writing of each address within the address range corresponding to a memory block n. When an address ni is designated with an addressing signal, a memory cell M(ni) corresponding to address ni is designated with an address decoder 14 and data is written to the M(ni). When the data is written to M(ni), condition of data V(ni) held by the valid cell corresponding to such address changes and V(ni) is switched to '1' from '0'. When data is written at least to one of the memories from M(n1) to M(ni), it can be determined and detected that data exists in the memory block n.

    ASSOCIATIVE MEMORY (CAM)
    23.
    发明专利
    ASSOCIATIVE MEMORY (CAM) 失效

    公开(公告)号：JP2000132978A

    公开(公告)日：2000-05-12

    申请号：JP30812198

    申请日：1998-10-29

    Applicant: IBM

    Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

    IPC: G11C7/00 ,  G11C15/00 ,  G11C15/04

    Abstract: PROBLEM TO BE SOLVED: To speed up a memory and reduce a consumption power by setting a first and a second switches which are turned on and off between an invertor output and a bit line in accordance with a signal on a word line and, a third and a fourth switches which are turned on and off between the bit line and a bit match node in accordance with an invertor output signal. SOLUTION: A voltage amplitude of a word match line 20 is restricted in a range between a higher potential by a threshold voltage of a PMOS transistor with a back gate bias from a ground potential and a lower potential by a threshold of an NMOS transistor NC: 41 with a back gate bias from a power source potential. The range can be made smaller. Accordingly, the voltage amplitude of the word match line 20 becomes small and a consumption power is reduced. When a precharge potential of the word match line 20 is lowered, boosting a bit line is eliminated although the NMOS transistor is used and a high-speed performance is ensured.

    SEMICONDUCTOR MEMORY, METHOD OF READING DATA FROM THE SEMICONDUCTOR MEMORY AND WRITING IT THEREIN
    24.
    发明专利
    SEMICONDUCTOR MEMORY, METHOD OF READING DATA FROM THE SEMICONDUCTOR MEMORY AND WRITING IT THEREIN 失效

    公开(公告)号：JPH1166839A

    公开(公告)日：1999-03-09

    申请号：JP21275897

    申请日：1997-08-07

    Applicant: IBM

    Inventor： TANAKA MASAHIRO ,  MIYATAKE HISATADA ,  MORI YOTARO ,  YAMAZAKI NORITOSHI

    IPC: G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/41

    Abstract: PROBLEM TO BE SOLVED: To improve a data transfer rate by transferring data plural times in one memory cycle. SOLUTION: A bit line of a memory array l is grouped based on a remainder when the row addresses are divided by the number of groups, and a row address decoding part 4 composing a bit line selection means 3 generates row addresses of the number corresponding to the number of groups according to the row address signal and an access order signal showing the order of the access to the group, and those bit lines are selected by a bit switch 5. Plural latch parts 6a, 6b, 6c each is provided for each group, and the bit line selection means 3 generates plural row addresses consecutive in the same direction referring to the row address signal corresponding to the access order signal.

    Pulse width adjustment circuit and method
    25.
    发明专利
    Pulse width adjustment circuit and method 有权
    脉冲宽度调整电路和方法

    公开(公告)号：JP2013118494A

    公开(公告)日：2013-06-13

    申请号：JP2011264819

    申请日：2011-12-02

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： ISHII MASATOSHI ,  MIYATAKE HISATADA ,  YAMADA GEN

    IPC: H03K5/06 ,  H03K5/1532

    CPC classification number: H03K3/017 ,  H03K5/04

    Abstract: PROBLEM TO BE SOLVED: To provide a pulse width adjustment circuit and method which reduce a leading edge delay of a pulse-width-adjusted pulse signal.SOLUTION: A pulse width adjustment circuit 300 includes: a pulse delay circuit 310 for receiving an input pulse signal a to output a plurality of different delayed pulse signals b1, b2, ...; a transmission gate 320 for receiving the input pulse signal a and controlling the passage of the input pulse signal a in response to the application of two of the plurality of different delayed pulse signals b1, b2, ...; and a pulse width setting circuit 330 connected to an output of the transmission gate 320 to set a pulse width of an output pulse signal c generated on the basis of the input pulse signal a passed through the transmission gate 320.

    Abstract translation: 要解决的问题：提供一种减小脉冲宽度调整脉冲信号的前沿延迟的脉宽调整电路和方法。 脉冲宽度调整电路300包括：脉冲延迟电路310，用于接收输入脉冲信号a以输出多个不同的延迟脉冲信号b1，b2，...; 传输门320，用于接收输入脉冲信号a并响应于多个不同的延迟脉冲信号b1，b2，...中的两个的应用来控制输入脉冲信号a的通过; 以及脉冲宽度设定电路330，连接到传输门320的输出端，以设定基于通过传输门320的输入脉冲信号a产生的输出脉冲信号c的脉冲宽度。 C）2013，JPO＆INPIT

    Asynchronous semiconductor memory device
    26.
    发明专利
    Asynchronous semiconductor memory device 有权
    异步半导体存储器件

    公开(公告)号：JP2008034082A

    公开(公告)日：2008-02-14

    申请号：JP2007124077

    申请日：2007-05-09

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MIYATAKE HISATADA

    IPC: G11C11/403 ,  G11C11/4076

    CPC classification number: G11C11/406 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/061

    Abstract: PROBLEM TO BE SOLVED: To provide an asynchronous pseudo SRAM which has compatibility with an asynchronous SRAM.
    SOLUTION: The asynchronous pseudo SRAM has a memory cell array 11 including dynamic memory cells 18; an array control circuit 12 for controlling reading or writing with an access enable signal bAE, and generating a busy signal bBUSY; an ATD circuit 19 for generating an address transition detecting signal ATD; an access request signal generating circuit 20 for generating an access request signal ARP with a chip enable signal bCE, a write enable signal bWE, and the address transition detecting signal ATD; an access waiting circuit 21 for controlling an access waiting signal bECP with the access request signal and the access enable signal; an access starting up circuit 15 for controlling the access enable signal with the access waiting signal and the busy signal; an OR circuit 16 for indicating acquisition of input data and so forth; and a latch circuit 17 for latching the address and so forth with the access enable signal.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供与异步SRAM兼容的异步伪SRAM。 解决方案：异步伪SRAM具有包括动态存储器单元18的存储单元阵列11; 阵列控制电路12，用于通过访问使能信号bAE控制读取或写入，并产生忙信号bBUSY; 用于产生地址转换检测信号ATD的ATD电路19; 访问请求信号发生电路20，用于产生具有芯片使能信号bCE的访问请求信号ARP，写使能信号bWE和地址转换检测信号ATD; 访问等待电路21，用于利用访问请求信号和访问使能信号来控制访问等待信号bECP; 访问启动电路15，用于利用访问等待信号和忙信号来控制访问使能信号; 用于指示获取输入数据等的OR电路16; 以及用于用访问使能信号来锁存地址等的锁存电路17。 版权所有（C）2008，JPO＆INPIT

    TRANSPORT SYSTEM AND METHOD THEREFOR
    27.
    发明专利
    TRANSPORT SYSTEM AND METHOD THEREFOR 审中-公开

    公开(公告)号：JP2003151086A

    公开(公告)日：2003-05-23

    申请号：JP2001336710

    申请日：2001-11-01

    Applicant: IBM

    Inventor： MIYATAKE HISATADA

    IPC: G06Q50/28 ,  G01S19/14 ,  G06Q10/08 ,  G06Q50/00 ,  G08G1/13 ,  H04W4/04 ,  G01S5/14 ,  G06F17/60 ,  H04Q7/34 ,  H04Q7/38

    Abstract: PROBLEM TO BE SOLVED: To provide a transport system and a method therefor allowing to normally trace a cargo without a need to make a record when transshipping the cargo. SOLUTION: This system includes a tag 12 fixed on the cargo, a center device 14 for collecting cargo position data and a communication network 16 for communicating between the tag 12 and the center device 14. A position detection means 18 is fixed on the tag 12 for detecting the position and the cargo 34 on which the tag 12 is fixed can be monitored by transmitting the position data to the center device 14.

    Memory cell, storage circuit block, data write-in method, and data read-out method
    28.
    发明专利
    Memory cell, storage circuit block, data write-in method, and data read-out method 有权
    存储单元，存储电路块，数据写入方法和数据读出方法

    公开(公告)号：JP2003016776A

    公开(公告)日：2003-01-17

    申请号：JP2001193984

    申请日：2001-06-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

    IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell, a storage circuit block, and a data write-n method in which a current value made to flow in a bit line at the time of write-in of data is reduced, further, to provide a memory cell, a storage circuit block, and a data read-out method in which parasitic resistance of a switching element or the like at the time of read-out of data is reduced. SOLUTION: The MRAM 10 comprises a second switching element connecting first wiring structure 18 and an adjacent memory cell 12 in a memory cell 12, and second wiring structure body 20. Also, a third switching element is provided between the second wiring structure body 20 and ground.

    Abstract translation: 要解决的问题：提供一种存储单元，存储电路块和数据写入方法，其中在数据写入时在位线中流动的当前值减小，此外，为了 提供存储单元，存储电路块和数据读出方法，其中在读出数据时开关元件等的寄生电阻减小。 解决方案：MRAM 10包括将第一布线结构18和相邻的存储单元12连接在存储单元12中的第二开关元件和第二布线结构体20.另外，第三开关元件设置在第二布线结构体20和 地面。

    SEMICONDUCTOR DEVICE, AND METHOD FOR TESTING SEMICONDUCTOR DEVICE
    30.
    发明专利
    SEMICONDUCTOR DEVICE, AND METHOD FOR TESTING SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JP2002042489A

    公开(公告)日：2002-02-08

    申请号：JP2000211898

    申请日：2000-07-12

    Applicant: IBM

    Inventor： MIYATAKE HISATADA ,  MORI YOTARO ,  TANAKA MASAHIRO

    IPC: G01R31/28 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/56

    Abstract: PROBLEM TO BE SOLVED: To eliminate a redundant test step in a test of retrieving operation of an associative memory having a priority encoder. SOLUTION: First, data being different from test data are written as background data (step 21). The background data are read out (step 22), and read-out data are tested (step 23). An address having the lowest priority is specified (step 26), and test data are written (step 27). Retrieving operation is performed (step 28), and it is discriminated whether the test address coincides with the retrieving address. Then, an address having low priority is specified (step 26), and the operation described above is repeated for all addresses (step 32).

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