公开(公告)号：DE3570556D1

公开(公告)日：1989-06-29

申请号：DE3570556

申请日：1985-07-12

Applicant: IBM

Inventor： CODELLA CHRISTOPHER FRANK ,  OGURA SEIKI

IPC: H01L21/265 ,  H01L21/338 ,  H01L29/08 ,  H01L29/10 ,  H01L29/812 ,  H01L29/80

公开(公告)号：DE3474742D1

公开(公告)日：1988-11-24

申请号：DE3474742

申请日：1984-11-06

Applicant: IBM

Inventor： OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/8222 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L21/60

Abstract: Methods for producing integrated circuit structures are described with reference to a small area lateral bipolar transistor comprising a semiconductor body (10) having surface regions thereof isolated from other such regions by a pattern of dielectric isolation. At least two narrow width PN junction regions are located within at least one of the surface regions. Substantially vertical conformal conductive layers (62, 64) electrically contact each of the PN junction regions which serve as the emitter (56) and collector (58) regions for the bipolar transistor. A junction base region (74) of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers (22) are in electrical contact with an edge of each of the vertical conductive layers (62, 64) and separated from the surface regions by a first electrically insulating layer (20). A second insulating layer (70) covers the conformal conductive layers. The horizontal conductive layer is patterned so as to form conductive lines electrically separated from one another. A third insulating layer (24) is located over the patterned horizontal conductive layers. An ohmic contact (80, 84) is made to each of the horizontal conductive layers (22) through an opening in the third insulating layer (24) which effectively makes electrical contacts to the emitter (56) and collector (58) regions via the patterned horizontal conductive layers (22) and the vertical conductive layers (62, 64). Another contact (82) is made to the base region (74) which contact is separated from the vertical conductive layers (62, 64) by the second insulating layer (70).

公开(公告)号：DE3174982D1

公开(公告)日：1986-08-28

申请号：DE3174982

申请日：1981-10-09

Applicant: IBM

Inventor： OGURA SEIKI ,  TSANG PAUL J

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78 ,  H01L21/265

Abstract: A method of manufacturing LDD MOS FET RAM capable of delineating short (less than 1 micrometer) lightly doped drain regions. An N- implant is effected between gate electrodes and field oxide insulators, before the N+ implant. An insulator layer is then deposited also prior to N+ ion implantation. Reactive ion etching of the layer leaves narrow dimensioned insulator regions adjacent the gate electrode which serves to protect portions of the N- impurity region during the subsequent N+ implant. These protected regions are the lightly doped source/drain regions.

公开(公告)号：DE3784958D1

公开(公告)日：1993-04-29

申请号：DE3784958

申请日：1987-01-23

Applicant: IBM

Inventor： DALLY ANTHONY JOHN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L21/225

Abstract: A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

公开(公告)号：DE3688042D1

公开(公告)日：1993-04-22

申请号：DE3688042

申请日：1986-10-10

Applicant: IBM

Inventor： OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO ,  SCHULZ RONALD N

IPC: G03F1/00 ,  G03F1/08 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/00 ,  H01L21/76

公开(公告)号：CA1245373A

公开(公告)日：1988-11-22

申请号：CA529768

申请日：1987-02-16

Applicant: IBM

Inventor： DALLY ANTHONY J ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/04

Abstract: Sidewall Spacers For CMOS Circuit Stress Relief Isolation And Method For Making A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

公开(公告)号：CA1244145A

公开(公告)日：1988-11-01

申请号：CA529470

申请日：1987-02-11

Applicant: IBM

Inventor： BALASUBRAMANYAM KARANAM ,  DALLY ANTHONY J ,  RISEMAN JACOB ,  OGURA SEIKI

IPC: H01L21/3205 ,  G03F7/09 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/72

Abstract: Disclosed is a process of forming high density, planar, single- or multi-level wiring for an semiconductor integrated circuit chip. On the chip surface is provided a dual layer of an insulator and hardened photoresist having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer of a thickness equal to that o. the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist is formed filling the metal valleys and obtaining a substantially planar surface. The lower component layer is thin and conformal and has a higher etch rate than the upper component layer which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photoresist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring. When only narrow wiring is desired, a single photoresist layer is substituted for the dual photoresist sacrificial layer.

公开(公告)号：DE69302960T2

公开(公告)日：1996-12-12

申请号：DE69302960

申请日：1993-03-23

Applicant: IBM

Inventor： DOERRE GEORGE WILLIAM ,  OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84 ,  H01L21/302

Abstract: An SOI wafer (10/20) has an epitaxial device layer (30) of initial thickness that is formed into a set of mesas (40) in the interval between which a temporary layer (42) of polysilicon is blanket deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop pads (45) (having a thickness greater than the initial thickness) except on the mesa side walls. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide forming pads (45) is not removed but serves both as an isolating layer to provide dielectric isolation between final mesas (40') in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.

公开(公告)号：DE68926224T2

公开(公告)日：1996-10-10

申请号：DE68926224

申请日：1989-11-07

Applicant: IBM

Inventor： OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L21/82

Abstract: A method for fabricating a Bi-CMOS device including both vertical PNP and NPN components. The process steps include forming the reach-through N+ subcollector to the bipolar device without extra processing steps; combining into one mask the threshold adjust/well implants with self-aligned isolation leakage protection implants by using a self-aligned, removable oxide mask prior to field isolation; using a resist etch-back scheme to protect against emitter-to-base punch-through while self-aligning the pedestal and base; and also providing for the removal of the gate oxide at the emitter while maintaining it at the FET, without extra masks. The device incorporates similar structural features between the bi-polar and FET devices. The NPN and PFET can share the same well and a P+ diffusion (the P+ extrinsic base is the same as the P+ source). Also, the PNP and NFET can share the same well and an N+ diffusion.

公开(公告)号：DE68926224D1

公开(公告)日：1996-05-15

申请号：DE68926224

申请日：1989-11-07

Applicant: IBM

Inventor： OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L21/82

Abstract: A method for fabricating a Bi-CMOS device including both vertical PNP and NPN components. The process steps include forming the reach-through N+ subcollector to the bipolar device without extra processing steps; combining into one mask the threshold adjust/well implants with self-aligned isolation leakage protection implants by using a self-aligned, removable oxide mask prior to field isolation; using a resist etch-back scheme to protect against emitter-to-base punch-through while self-aligning the pedestal and base; and also providing for the removal of the gate oxide at the emitter while maintaining it at the FET, without extra masks. The device incorporates similar structural features between the bi-polar and FET devices. The NPN and PFET can share the same well and a P+ diffusion (the P+ extrinsic base is the same as the P+ source). Also, the PNP and NFET can share the same well and an N+ diffusion.