公开(公告)号：DK2248025T3

公开(公告)日：2012-05-07

申请号：DK09714687

申请日：2009-02-17

Applicant: IBM

Inventor： GREINER DAN ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN

IPC: G06F12/10

公开(公告)号：AT460704T

公开(公告)日：2010-03-15

申请号：AT06777769

申请日：2006-07-13

Applicant: IBM

Inventor： ADLUNG INGO ,  CHOI JONG ,  FRANKE HUBERTUS ,  HELLER LISA ,  HOLDER WILLIAM ,  MANSELL RAY ,  OSISEK DAMIAN ,  PHILLEY RANDALL ,  SCHWIDEFSKY MARTIN ,  SITTMANN GUSTAV

IPC: G06F9/50 ,  G06F9/455

公开(公告)号：AU2022287210B2

公开(公告)日：2024-12-12

申请号：AU2022287210

申请日：2022-05-31

Applicant: IBM

Inventor： GIAMEI BRUCE ,  SLEGEL TIMOTHY ,  BORNTRAEGER CHRISTIAN ,  OSISEK DAMIAN ,  HELLER LISA ,  GAERTNER UTE ,  YOST CHRISTINE ,  TZORTZATOS ELPIDA

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14

Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

公开(公告)号：MX2023013910A

公开(公告)日：2023-12-08

申请号：MX2023013910

申请日：2022-05-31

Applicant: IBM

Inventor： HELLER LISA ,  SLEGEL TIMOTHY ,  BORNTRAEGER CHRISTIAN ,  GIAMEI BRUCE ,  OSISEK DAMIAN ,  GAERTNER UTE ,  YOST CHRISTINE ,  TZORTZATOS ELPIDA

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/14

Abstract: Se proporciona una instrucción para llevar a cabo una operación de reinicio de protección de traducción de dirección cuando se ejecuta. Ejecutar la instrucción incluye determinar, por medio de un procesador, que se va a reiniciar un bit de protección de traducción de dirección en una entrada de tabla de traducción especificada asociada con un bloque de almacenamiento. Con base en la determinación de que se va a reiniciar el bit de protección de traducción de dirección, ejecutar la instrucción incluye reiniciar el bit de protección de traducción de dirección para desactivar la protección contra escritura para el bloque de almacenamiento. El reinicio no espera una acción por uno o más de otros procesadores del entorno de cómputo.

公开(公告)号：HRP20211545T3

公开(公告)日：2022-01-07

申请号：HRP20211545

申请日：2009-02-16

Applicant: IBM

Inventor： SZWED PETER KENNETH ,  OSISEK DAMIAN ,  HELLER LISA ,  FARRELL MARK ,  GAINEY CHARLES ,  GREINER DAN

IPC: G06F11/07 ,  G06F12/14

公开(公告)号：PL2248020T3

公开(公告)日：2021-12-27

申请号：PL09714605

申请日：2009-02-16

Applicant: IBM

Inventor： SZWED PETER KENNETH ,  OSISEK DAMIAN ,  HELLER LISA ,  FARRELL MARK ,  GAINEY JR CHARLES ,  GREINER DAN

IPC: G06F12/14 ,  G06F11/07

公开(公告)号：SI2248020T1

公开(公告)日：2021-11-30

申请号：SI200932144

申请日：2009-02-16

Applicant: IBM

Inventor： SZWED PETER KENNETH ,  OSISEK DAMIAN ,  HELLER LISA ,  FARRELL MARK ,  GAINEY JR CHARLES ,  GREINER DAN

IPC: G06F12/00 ,  G06F11/00

公开(公告)号：HUE046174T2

公开(公告)日：2020-02-28

申请号：HUE15763327

申请日：2015-09-14

Applicant: IBM

Inventor： HELLER LISA ,  BUSABA FADI ,  BRADBURY JONATHAN ,  FARRELL MARK ,  GREINER DAN ,  KUBALA JEFFREY ,  OSISEK DAMIAN ,  SLEGEL TIMOTHY ,  SCHMIDT DONALD

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/46 ,  G06F9/48

公开(公告)号：CA2701086C

公开(公告)日：2017-09-19

申请号：CA2701086

申请日：2009-01-05

Applicant: IBM

Inventor： GREINER DAN ,  GAINEY JR CHARLES ,  HELLER LISA ,  OSISEK DAMIAN ,  SLEGEL TIMOTHY ,  SITTMANN III GUSTAV

IPC: G06F9/30 ,  G06F12/1009 ,  G06F12/14

Abstract: What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.

公开(公告)号：AU2015330266A1

公开(公告)日：2017-03-09

申请号：AU2015330266

申请日：2015-09-14

Applicant: IBM

Inventor： FARRELL MARK ,  HELLER LISA ,  KUBALA JEFFREY PAUL ,  SCHMIDT DONALD WILLIAM ,  GREINER DAN ,  SLEGEL TIMOTHY ,  BUSABA FADI YUSUF ,  OSISEK DAMIAN ,  BRADBURY JONATHAN DAVID ,  LEHNERT FRANK ,  NERZ BERND ,  JACOBI CHRISTIAN

IPC: G06F9/455 ,  G06F9/48

Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.