23.
    发明专利
    未知

    公开(公告)号:ES2075837T3

    公开(公告)日:1995-10-16

    申请号:ES89110424

    申请日:1989-06-09

    Applicant: IBM

    Abstract: Heterostructures (20) having a large lattice mismatch between an upper epilayer (24) and a substrate (22) and a method of forming such structures having a thin intermediate layer (26) are disclosed. The strain due to a lattice mismatch between the intermediate layer (26) and the substrate (22) is partially relieved by the formation of edge type dislocations (15) which are localized and photoelectrically inactive. Growth of the intermediate layer (26) is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer (24) is then grown in an unstrained and defect-free condition upon the intermediate layer (26) where the unstrained lattice constant (aL2) of the epilayer (24) is about the same as the partially relieved strain lattice constant (aL1) of the intermediate layer (26). An unstrained defect-free epilayer (24) of InGaAs has been grown on a GaAs substrate (22) with an intermediate layer (26) 3-10 nm in thickness of InAs. Other large mismatch systems are disclosed, including, GaAs on Si with an intermediate layer (26) of GaInAs.

    24.
    发明专利
    未知

    公开(公告)号:DE68923920D1

    公开(公告)日:1995-09-28

    申请号:DE68923920

    申请日:1989-06-09

    Applicant: IBM

    Abstract: Heterostructures (20) having a large lattice mismatch between an upper epilayer (24) and a substrate (22) and a method of forming such structures having a thin intermediate layer (26) are disclosed. The strain due to a lattice mismatch between the intermediate layer (26) and the substrate (22) is partially relieved by the formation of edge type dislocations (15) which are localized and photoelectrically inactive. Growth of the intermediate layer (26) is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer (24) is then grown in an unstrained and defect-free condition upon the intermediate layer (26) where the unstrained lattice constant (aL2) of the epilayer (24) is about the same as the partially relieved strain lattice constant (aL1) of the intermediate layer (26). An unstrained defect-free epilayer (24) of InGaAs has been grown on a GaAs substrate (22) with an intermediate layer (26) 3-10 nm in thickness of InAs. Other large mismatch systems are disclosed, including, GaAs on Si with an intermediate layer (26) of GaInAs.

    SEMICONDUCTOR OHMIC CONTACT
    25.
    发明专利

    公开(公告)号:CA1166764A

    公开(公告)日:1984-05-01

    申请号:CA377196

    申请日:1981-05-08

    Applicant: IBM

    Inventor: WOODALL JERRY M

    Abstract: YO980-032 SEMICONDUCTOR OHMIC CONTACT An ohmic contact to intermetallic semiconductors with a resistance of much less than 10-6 ohm cm2 can be provided by introducing between the semiconductor and an external metal contact an atomically compatible barrier-free graded layer of a conductor having at the interface with a metal external contact an energy gap width of the semiconductor less than 0.5 electron volts. An ohmic contact for gallium arsenide can be provided by a graded region of indium gallium arsenide that decreases to indium arsenide at the interface with a metal.

    SEMICONDUCTOR DEVICE FABRICATION
    26.
    发明专利

    公开(公告)号:CA1155970A

    公开(公告)日:1983-10-25

    申请号:CA358895

    申请日:1980-08-25

    Applicant: IBM

    Abstract: Semiconductor devices can be fabricated using as an intermediate manufacturing structure a substrate of one semiconductor with a thin epitaxial surface layer of a different semiconductor with properties such that the semiconductors each have different solubilities with respect to a metal. When a vertical differentiation is used to expose the different materials and the metal is deposited on both and heated, the metal will form a Schottky barrier in one material and an ohmic contact in the other. Where the substrate is gallium arsenide and the epitaxial layer is gallium aluminum arsenide and the metal is tin, a self-aligned gallium arsenide MESFET is formed wherein the tin forms ohmic contacts with the gallium arsenide and a Schottky barrier contact with the gallium aluminum arsenide.

    LUMINOUS ENERGY CONVERTER
    27.
    发明专利

    公开(公告)号:HU172031B

    公开(公告)日:1978-05-28

    申请号:HUIE000717

    申请日:1975-10-17

    Applicant: IBM

    Abstract: An efficient converter of photon energy to heat has been devised comprising a dense array of metal whiskers grown with spacings between the whiskers of a few wavelengths of visible light. The material selected, and tungsten is exemplary of such materials, has low emissivity, but achieves significant optical absorption by trapping the light impinging on the dense array by a geometric maze effect. The characteristics of the surface are excellent for the conversion of solar energy to heat.

    28.
    发明专利
    未知

    公开(公告)号:FR2346821A1

    公开(公告)日:1977-10-28

    申请号:FR7525826

    申请日:1975-08-11

    Applicant: IBM

    Abstract: An efficient converter of photon energy to heat has been devised comprising a dense array of metal whiskers grown with spacings between the whiskers of a few wavelengths of visible light. The material selected, and tungsten is exemplary of such materials, has low emissivity, but achieves significant optical absorption by trapping the light impinging on the dense array by a geometric maze effect. The characteristics of the surface are excellent for the conversion of solar energy to heat.

    29.
    发明专利
    未知

    公开(公告)号:FR2295575A1

    公开(公告)日:1976-07-16

    申请号:FR7533264

    申请日:1975-10-20

    Applicant: IBM

    Abstract: A process for producing light emitting diodes is disclosed. In the process a primer layer of GaP is pyrolytically deposited on a Si substrate with the resulting epitaxial film thickness being sufficient to form complete coalescence of the epitaxial nuclei, but thin enough to avoid cracks in the epitaxial layer due to stress induced by thermal expansion. The thickness is generally between 1-2 mu . A second layer of GaP is then deposited using the standard halide transport process with thicknesses of 10-20 mu with the graded addition of AsH3, until the particularly desired design composition of GaAsP is obtained. A constant layer of GaAsP is grown on the graded layer.

    30.
    发明专利
    未知

    公开(公告)号:DE68923920T2

    公开(公告)日:1996-04-18

    申请号:DE68923920

    申请日:1989-06-09

    Applicant: IBM

    Abstract: Heterostructures (20) having a large lattice mismatch between an upper epilayer (24) and a substrate (22) and a method of forming such structures having a thin intermediate layer (26) are disclosed. The strain due to a lattice mismatch between the intermediate layer (26) and the substrate (22) is partially relieved by the formation of edge type dislocations (15) which are localized and photoelectrically inactive. Growth of the intermediate layer (26) is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer (24) is then grown in an unstrained and defect-free condition upon the intermediate layer (26) where the unstrained lattice constant (aL2) of the epilayer (24) is about the same as the partially relieved strain lattice constant (aL1) of the intermediate layer (26). An unstrained defect-free epilayer (24) of InGaAs has been grown on a GaAs substrate (22) with an intermediate layer (26) 3-10 nm in thickness of InAs. Other large mismatch systems are disclosed, including, GaAs on Si with an intermediate layer (26) of GaInAs.

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