公开(公告)号：DE602006008984D1

公开(公告)日：2009-10-15

申请号：DE602006008984

申请日：2006-12-05

Applicant: IBM

Inventor： MANDELMAN JACK ALLAN ,  CHENG KANGGUO ,  HSU LOUIS LU-CHEN ,  YANG HAINING

IPC: H01L29/786 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/78

Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

公开(公告)号：AT437449T

公开(公告)日：2009-08-15

申请号：AT06824840

申请日：2006-08-22

Applicant: IBM

Inventor： YANG HAINING

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49

公开(公告)号：SG122926A1

公开(公告)日：2006-06-29

申请号：SG200507470

申请日：2005-11-24

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： CHAN VICTOR W ,  LEE YONG M ,  YANG HAINING

公开(公告)号：AT504078T

公开(公告)日：2011-04-15

申请号：AT04780054

申请日：2004-08-04

Applicant: IBM

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/20 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

Abstract: A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

公开(公告)号：SG121981A1

公开(公告)日：2006-05-26

申请号：SG200506629

申请日：2005-10-12

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： YANG HAINING ,  LIM ENG HUA

Abstract: A method for improving hot carrier effects in complementary metal oxide semiconductor (CMOS) devices includes forming a first configuration of insulating material over a first group of the CMOS devices, and forming a second configuration of insulating material over a second group of the CMOS devices. The first and said second configurations of insulating material are formed subsequent to a silicidation of the CMOS devices and prior to formation of a first interlevel (ILD) dielectric material over the CMOS devices.