公开(公告)号：EP0794567A3

公开(公告)日：2000-01-12

申请号：EP97102901

申请日：1997-02-21

Applicant: SIEMENS AG ,  IBM

Inventor： HO HERBERT L ,  SRINIVASAN RADHIKA ,  HALLE SCOTT D ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  MANDELMAN JACK A ,  JASO MARK ANTHONY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10861 ,  H01L21/76232 ,  H01L27/10832 ,  H01L28/82 ,  Y10S438/973

Abstract: A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.

公开(公告)号：EP1588403A4

公开(公告)日：2010-03-24

申请号：EP04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

公开(公告)号：EP1584108A4

公开(公告)日：2006-06-07

申请号：EP03701269

申请日：2003-01-08

Applicant: IBM

Inventor： MANDELMAN JACK A ,  GAMBINO JEFFREY P ,  WANG GENG

IPC: H01L21/20 ,  H01L21/308 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3081 ,  H01L27/10864

Abstract: Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

公开(公告)号：EP0720218A3

公开(公告)日：1998-12-16

申请号：EP95119309

申请日：1995-12-07

Applicant: SIEMENS AG ,  IBM

Inventor： ALSMEIER JOHANN ,  MANDELMAN JACK A

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L29/78 ,  H01L21/76 ,  H01L29/10

CPC classification number: H01L27/10873 ,  H01L21/823412 ,  H01L29/7838

Abstract: Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850°C gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850°C gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850°C gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850°C gate oxidation step may follow the RTO gate oxidation step.

Abstract translation: 如动态随机存取存储器（DRAM）技术中，用于显着地减少到设备异常埋沟道p-MOSFET灵敏度制造沟槽界定埋沟p型金属氧化物半导体场效应晶体管（P-MOSFET）的，的方法 宽度。 在一个实施方式中，该方法包括深磷n阱注入步骤之后，使用惰性气体的低温退火步骤的开始，和硼埋沟道注入之前和850℃栅极氧化步骤。 可替代地，退火步骤可以在硼埋沟植入物和850℃栅极氧化步骤之前，之后进行。 在另一个实施方式快速热氧化（RTO）的步骤代替了850℃栅极氧化步骤，继深磷n阱和硼埋入沟道注入步骤。 可替换地，在850℃下栅极氧化步骤可跟随RTO栅极氧化步骤。

公开(公告)号：WO2007082227A3

公开(公告)日：2008-09-25

申请号：PCT/US2007060317

申请日：2007-01-10

Applicant: IBM ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory (100) having multiple ports per memory cell for accessing a data bit with each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plural of capacitors (102) connected together as a unitary source of capacitance (S). A first access transistor (104) is coupled between a firs one of the plurality of capacitors and a first bitline (RBL) and a second access transistor (106) is coupled between a second one of th plurality of capacitors and a second bitline (WBL) In each memory cell, a gate of the first access transistor (104) is connected to a fi wordline (RWL) and a gate of the second access transistor (106) is connected to a second wordline (WWL)

Abstract translation: 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器（100），用于利用多个存储器单元中的每一个访问数据位。 这样的存储器包括存储单元阵列，其中每个存储单元包括连接在一起的多个电容器（102）作为电容（S）的整体源。 第一存取晶体管（104）耦合在所述多个电容器中的第一个电容器中，并且第一位线（RBL）和第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线（WBL ）在每个存储单元中，第一存取晶体管（104）的栅极连接到fi字线（RWL），第二存取晶体管（106）的栅极连接到第二字线（WWL）

公开(公告)号：WO2004066367A3

公开(公告)日：2009-05-28

申请号：PCT/US2004000968

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/76 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

Abstract: A low-GIRL current MOSFET device (90) structure and a method of fabrication thereof which provides a low-GIRL current. The MOSFET device structure contains a central gate conductor (10) whose edges may slightly overlap the source/drain diffusions (88, 88), and left and right side wing gate conductors (70,70) which are separated from the central gate conductor by a thin insulating and diffusion barrier layer (50, 52).

Abstract translation: 低GIRL电流MOSFET器件（90）结构及其制造方法，其提供低GIRL电流。 MOSFET器件结构包含中心栅极导体（10），其边缘可能与源极/漏极扩散（88,88）稍微重叠，并且左右翼栅极导体（70,70）与中心栅极导体分开， 薄的绝缘和扩散阻挡层（50,52）。

公开(公告)号：JP2007243176A

公开(公告)日：2007-09-20

申请号：JP2007039055

申请日：2007-02-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TONTI WILLIAM R ,  MANDELMAN JACK A ,  HSU LOUIS LU-CHEN ,  WILLIAM P HOVIS ,  YANG CHIH-CHAO

IPC: H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an electrically programmable fuse structure for IC, and its manufacturing method. SOLUTION: This electrically programmable fuse has a first terminal part and second terminal part that are interconnected with fuse and elements. The first terminal part and second terminal part exist in different heights to the support surface of the fuse structure. The interconnecting fuse element connects the height difference between the height of the first terminal part and the second terminal part. While the first terminal part and second terminal part are oriented to be parallel with the support surface, the fuse element include a part oriented to be a right angle to the support surface, and also include at least one right-angled curvature portion that connects at least one of the first terminal element and second terminal element and the part of the fuse element oriented to be right angle. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为IC提供电可编程熔丝结构及其制造方法。 解决方案：该电可编程熔丝具有与熔丝和元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分与熔丝结构的支撑表面存在不同的高度。 互连保险丝元件连接第一端子部分和第二端子部分的高度之间的高度差。 当第一端子部分和第二端子部分被取向为与支撑表面平行时，熔丝元件包括定向成与支撑表面成直角的部分，并且还包括至少一个直角曲率部分，其连接在 第一端子元件和第二端子元件中的至少一个和熔丝元件的一部分被定向为直角。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007150317A

公开(公告)日：2007-06-14

申请号：JP2006317746

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOBUZINSKY DAVID M ,  HO HERBERT L ,  MANDELMAN JACK A ,  OTANI YOICHI

IPC: H01L21/8247 ,  H01L21/265 ,  H01L21/76 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is formed in a semiconductor-on-insulator (SOI) substrate. SOLUTION: A memory cell comprises: a semiconductor-on-insulator substrate including a top semiconductor layer and a bottom semiconductor layer that are separated from each other by a buried insulating layer; and at least one vertical trench SONOS memory cell located in the semiconductor-on-insulator substrate. The at least one vertical trench SONOS memory cell comprises: a source diffusion located beneath the vertical trench; a selection gate channel located on one side of the vertical trench; an outward-diffused/Si-containing bridge located on and in contact with the selection gate channel; and a silicided doped region located adjacent to and in contact with an upper portion of the bridge. The bridge is present in the top semiconductor layer, the buried insulating layer, and the bottom semiconductor layer. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元。 解决方案：存储单元包括：绝缘体上半导体衬底，包括通过掩埋绝缘层彼此分离的顶部半导体层和底部半导体层; 以及位于绝缘体上半导体衬底中的至少一个垂直沟道SONOS存储器单元。 所述至少一个垂直沟道SONOS存储单元包括：位于垂直沟槽下方的源极扩散; 位于所述垂直沟槽的一侧上的选择栅极沟道; 位于选择栅极通道上并与选择栅极通道接触的向外扩散/含Si桥; 以及位于与桥的上部相邻并与其接触的硅化物掺杂区域。 该桥存在于顶部半导体层，埋入绝缘层和底部半导体层中。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004193588A

公开(公告)日：2004-07-08

申请号：JP2003389984

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEWIS L SUU ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: G11C11/412 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM cell design capable of simultaneously attaining high performance, low power, and small chip size by using only vertical MOSFET device including a peripheral (transmission) gate. SOLUTION: A method for forming a SRAM cell device comprises the steps of forming a pass gate FET transistor in a silicon layer formed on a flat insulating material and a parallel island, and further forming a pair of vertical pulldown FET transistors having a first common body and a first common source region. The method further forms a pulldown separation space for dividing an upper layer of a pullup and pulldown drain region of a pair of vertical pulldown FET transistor in two by etching through the upper diffusion between cross-linked inverter FET transistors, and the separation space reaches the common boby layer. The method further comprises the steps of forming a pair of vertical pullup FET transistor having a second common body and a second common drain, and connecting the FET transistor so as to form a SRAM cell. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：通过仅使用包括外围（传输）门的垂直MOSFET器件，提供能够同时获得高性能，低功率和小芯片尺寸的SRAM单元设计。 解决方案：一种用于形成SRAM单元器件的方法包括以下步骤：在形成于平坦绝缘材料和平行岛上的硅层中形成栅极FET晶体管，并进一步形成一对垂直下拉FET晶体管，其具有 第一共同体和第一共同源区。 该方法进一步形成一个下拉分离空间，用于通过在交联的反相FET晶体管之间的上部扩散进行蚀刻，将一对垂直下拉式FET晶体管的上拉和下拉漏极区的上层分成两层，分离空间达到 普通boby层。 该方法还包括以下步骤：形成具有第二公共体和第二公共漏极的一对垂直上拉FET晶体管，并连接FET晶体管以形成SRAM单元。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JPH11258774A

公开(公告)日：1999-09-24

申请号：JP906799

申请日：1999-01-18

Applicant: IBM

Inventor： DONALD C WHEELER ,  MANDELMAN JACK A ,  REBECCA D MEA

IPC: G03F1/28 ,  G03F7/20 ,  H01L21/027 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To make it possible to control a resist pattern formed in manufacture by a pattern to be formed by providing a multilayer mask with a multiplex light phase shifting means for shifting phases of light so that light passing the mask has plural phases. SOLUTION: A base 11 for the mask 10 mounts a light shielding material 13 having a linear form on its surface. The multiplex light phase shifting means is arranged adjacently to one side of the material 13. A first channel 15 of height TP2 is arranged adjacently to an area 14. A second channel 16 of height TP3 is similarly arranged adjacently to the 1st channel 15. The phase shift of light to be passed is defined by these height values TP1 , TP2 , TP3 . Differences between the phase of light passing a part 12 of the mask substrate and the phases of light passing opposite side parts 14 to 16 should be values other than 0 deg., 180 deg. or their multiples in at least one, preferably two or more light phases.