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    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION
    21.
    发明申请
    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION 审中-公开
    通过光刻对齐和注册来实现硅通孔

    公开(公告)号：WO2011090852A2

    公开(公告)日：2011-07-28

    申请号：PCT/US2011020913

    申请日：2011-01-12

    Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

    Abstract translation: 制造集成电路结构的方法在衬底（100;图1）中形成第一开口并用保护性衬垫排列第一开口。 （102）该方法将材料沉积到第一开口（104）中并且在衬底上形成保护材料。 保护材料包括过程控制标记并且包括在第一开口上方并与第一开口对齐的第二开口。 （108）该方法通过保护材料中的第二开口从第一开口移除材料。 （110）过程控制标记包括保护材料内的凹部，其仅部分地延伸穿过保护材料，使得过程控制标记下方的部分基板不受移除材料的过程的影响。

    CMOS IMAGER OF ELIMINATING HIGH REFLECTIVITY INTERFACES
    22.
    发明申请
    CMOS IMAGER OF ELIMINATING HIGH REFLECTIVITY INTERFACES 审中-公开
    消除高反射性界面的CMOS图像

    公开(公告)号：WO2006071540A3

    公开(公告)日：2007-04-12

    申请号：PCT/US2005045328

    申请日：2005-12-14

    Applicant: IBM ,  ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

    Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

    IPC: H01L29/04

    CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    Abstract: An image sensor (20) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (135a, 135b) allowing for incorporation of a thinner interlevel dielectric stack (130a-130c) to result in a pixel array (100) exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal (132a, 132b) that traverses the optical path of each pixel in the sensor array or, that have portions (50) of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer (142) may be formed atop the Cu metallization by a self-aligned deposition.

    Abstract translation: 一种图像传感器（20）及其制造方法，其中传感器包括铜（Cu）金属化水平（135a，135b），允许结合更薄的层间电介质堆叠（130a-130c）以产生呈现增加的像素阵列（100） 光敏感。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属（132a，132b）的最小厚度的结构，或者具有从每个的光路中选择性地去除的阻挡层金属的部分（50） 像素，从而最小化反射率。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层（142）可以通过自对准沉积形成在Cu金属化之上。

    Bipolar transistor structure and manufacturing method therefor
    23.
    发明专利
    Bipolar transistor structure and manufacturing method therefor 有权
    双极晶体管结构及其制造方法

    公开(公告)号：JP2011003907A

    公开(公告)日：2011-01-06

    申请号：JP2010141326

    申请日：2010-06-22

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： STAMPER ANTHONY K ,  DAHLSTROM MATTIAS ERIK ,  BENOIT JOHN JOSEPH ,  GRAY PETER BRIAN ,  DUPUIS MARK DAVID

    IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737

    CPC classification number: H01L29/732 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L29/34 ,  H01L29/66272

    Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor structure with enhanced performance by optimizing junction interface characteristics between an emitter and a base, and a manufacturing method therefor.SOLUTION: The bipolar transistor includes: (1) a collector region 15 located at least in-part within a semiconductor substrate; (2) a base region 16 contacting the collector region; and (3) an emitter region 24 contacting the base region. A damaged region 16A that includes an oxygen impurity and at least one impurity selected from a group consisting of a fluorine impurity and a carbon impurity is formed in a layer 16 that includes a base of an emitter aperture at an interface between the emitter region and the base region, thus the performance of the bipolar transistor being enhanced. The impurities may be introduced into the interface by plasma etch treatment or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material composing the base region.

    Abstract translation: 要解决的问题：通过优化发射极和基极之间的结界面特性来提供具有增强性能的双极晶体管结构及其制造方法。解决方案：双极晶体管包括：（1）至少位于 在半导体衬底内; （2）与收集器区域接触的基极区域16; 和（3）与基极区域接触的发射极区域24。 包含氧杂质和选自氟杂质和碳杂质的至少一种杂质的受损区域16A形成在层16中，该层16包括在发射极区域和发射极区域之间的界面处的发射极孔径的基极 从而提高了双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或替代地进行后处理，然后进行无水氨和氟化氢处理，构成基区的基材。

    CAPACITOR STRUCTURE AND ITS MANUFACTURING METHOD
    25.
    发明专利
    CAPACITOR STRUCTURE AND ITS MANUFACTURING METHOD 失效

    公开(公告)号：JP2001313373A

    公开(公告)日：2001-11-09

    申请号：JP2001098235

    申请日：2001-03-30

    Applicant: IBM

    Inventor： KERRY BERNSTEIN ,  GEFFKEN ROBERT M ,  STAMPER ANTHONY K ,  STEVEN A SAINT ONGE

    IPC: H01L23/52 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To provide a metal capacitor installed on a chip. SOLUTION: Capacitors (60, 126) manufactured on a semiconductor chip have strap/contacts (41A, 119A), which mutually connect bottom plates (41B, 111A) of a capacitor to a chip circuit. In one version, an extension part of a material, constituting a bottom plate of a capacitor forms a strap contact. In the other version, a capacitor (185) comprises a folded bottom plate, which uses an available space and therefore increases its capacitance, a dielectric layer and a top plate. By means of a plurality of manufacturing methods, manufacturing of these capacitors of various versions can be incorporated in a standard dual or single-damascene manufacturing process, including a copper damascene process.

    MUTUAL CONNECTION USING METALLIC SPACER AND ITS MANUFACTURING METHOD
    26.
    发明专利
    MUTUAL CONNECTION USING METALLIC SPACER AND ITS MANUFACTURING METHOD 失效

    公开(公告)号：JPH10289949A

    公开(公告)日：1998-10-27

    申请号：JP9198298

    申请日：1998-04-03

    Applicant: IBM

    Inventor： CRONIN JOHN E ,  HARTSWICK THOMAS J ,  STAMPER ANTHONY K

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To facilitate mutual connection between a connecting wire and a mutual connection stud by using a sidewall spacer on the side face of the connecting wire for widening the contact area between the connecting wire and the connection stud. SOLUTION: A semiconductor part 100 has a connection stud 102 connecting the first connecting wire 104 to the second connecting wire 106. The first connecting wire 104 and the second connecting wire 106 and made of a metallic conductor in high conductivity. A substitute conductive path is formed between the first connecting wire 104 and the mutual connection stud 102 by a sidewall spacer 2 added to the first connecting wire 104 before an insulator is bonded. Especially, the side wall 22 comes into contact with a Ti/TiN layer 108 along the outer side thereof. Furthermore, the connection stud 102 is connected to the sidewall spacer 122 which is further connected to the first connecting wire 104. Accordingly, the sidewall spacer 122 is connected to the first connecting wire 104 along the whole sidewall thereof.

    CAPACITOR STRUCTURE AND ITS MANUFACTURING METHOD
    28.
    发明专利
    CAPACITOR STRUCTURE AND ITS MANUFACTURING METHOD 失效

    公开(公告)号：JP2001313372A

    公开(公告)日：2001-11-09

    申请号：JP2001090567

    申请日：2001-03-27

    Applicant: IBM

    Inventor： JENNIFER D LYNCH ,  WILBUR D PRISER ,  STAMPER ANTHONY K ,  STEVEN A SAINT ONGE

    IPC: H01L21/28 ,  H01L21/283 ,  H01L21/70 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/02 ,  H01L27/04 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable chip-on-capacitor. SOLUTION: The capacitor (94) in a semiconductor device (20) has a lower copper plate (30) in a damascene/trench (22), barrier layers (56, 180a) disposed above the lower plate, a dielectric layer (60) disposed above the barrier layers and an upper plate (96) above the dielectric layer. Another embodiment of this invention is capacitors (296, 396) in a semiconductor device, which has two lower plates (230, 231, 330, 331) mutually separated, dielectric layers (260, 360) above the lower plate and upper plates (296, 396) above the dielectric layer which covers the lower plate, extends preferably across it. This invention further includes a method for manufacturing the capacitor of such a constitution.

    METALLIC CAPACITOR AND ITS FORMATION METHOD
    29.
    发明专利
    METALLIC CAPACITOR AND ITS FORMATION METHOD 失效

    公开(公告)号：JP2001313371A

    公开(公告)日：2001-11-09

    申请号：JP2001073042

    申请日：2001-03-14

    Applicant: IBM

    Inventor： ROBERT M JEFFKEN ,  STAMPER ANTHONY K

    IPC: H01L21/3205 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To provide a metallic capacitor which is provided inside a metal layer on a semiconductor chip. SOLUTION: A lower plate of a capacitor is provided between an insulation layer and a dielectric layer. An insulation layer is disposed adjacent to a metallization layer, and a dielectric layer separates a lower plate of a capacitor from the upper plate of the capacitor. The shoulder part of a lower plate is adjacent to it and brought into contact with a via filled with copper. Although a via extends upward to a common surface of the upper plate, it is electrically isolated from an upper plate. A via also extends downward toward a metallization layer. This structure is formed by a copper dual-damascene process.

    STRUCTURE OF PRECISION CIRCUIT ELEMENT AND METHOD OF FORMING IT
    30.
    发明专利
    STRUCTURE OF PRECISION CIRCUIT ELEMENT AND METHOD OF FORMING IT 失效

    公开(公告)号：JP2001308280A

    公开(公告)日：2001-11-02

    申请号：JP2001070049

    申请日：2001-03-13

    Applicant: IBM

    Inventor： STEPHEN H BALDEMAN ,  STAMPER ANTHONY K

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L23/522 ,  H01L23/525 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To provide a precision circuit element and a method of forming it. SOLUTION: The circuit element is formed as one part of an integrated circuit assembly. The process of the circuit element provides a nominal value of the circuit element that is near to a desired value. An additional trim circuit element is coupled through a link to the nominal circuit element. The Link is a fusible link or an anti fuse. By fusing and cutting the fusible link selectively or by adding or reducing the trim circuit element by fusing the anti fuse, the nominal value of the circuit element is individuated. In a typical example, a capacitor is used.

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