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    Halbleiterstruktur mit Kondensator
    21.
    发明专利
    Halbleiterstruktur mit Kondensator 未知

    公开(公告)号：DE102009001522B4

    公开(公告)日：2016-03-10

    申请号：DE102009001522

    申请日：2009-03-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BARTH HANS-JOACHIM ,  TEWS HELMUT

    IPC: H01L25/16 ,  H01L21/58 ,  H01L21/60 ,  H01L27/06 ,  H01L29/92

    Abstract: Halbleiterstruktur (110) mit: einem Halbleiterchip (200), der zumindest teilweise in einer Trägervorrichtung (410) eingebettet ist, und einem Kondensator (300), der elektrisch an den Chip (200) gekoppelt ist, wobei der Kondensator (300) außerhalb der lateralen Begrenzung des Chips (200) angeordnet ist, mit einer leitenden Umverteilungsschicht (500), wobei die Umverteilungsschicht (500) einen ersten Teilbereich (500A) und einen zweiten Teilbereich (500B) beinhaltet, der mit Abstand von dem ersten Teilbereich (500A) angeordnet ist, wobei der erste Teilbereich (500A) einen ersten Teil hat, der eine erste Kondensatorplatte des Kondensators (300) bildet, wobei der erste Teilbereich (500A) einen zweiten Teil hat, der die erste, obere Kondensatorplatte elektrisch an den Chip (200) koppelt, wobei der zweite Teilbereich (500B) eine zweite, untere Kondensatorplatte (320) des Kondensators (300) elektrisch an den Chip (200) koppelt, wobei ein Kondensatordielektrikum (330) ein Material mit hohem k oder eine Kombination von verschiedenen dielektrischen Materialien umfasst.

    23.
    发明专利
    未知

    公开(公告)号：DE102009044955A1

    公开(公告)日：2010-04-22

    申请号：DE102009044955

    申请日：2009-09-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BARTH HANS-JOACHIM ,  BRUNNBAUER MARKUS ,  KOERNER HEINRICH ,  MEYER THORSTEN

    IPC: H01L23/66 ,  H01L21/768 ,  H01L23/522

    Abstract: Structure and method for fabricating a system on chip with an on-chip RF shield including interconnect metallization is described. In one embodiment, the system on chip includes an RF circuitry disposed on a first portion of a top surface of a substrate, and a semiconductor circuitry disposed on a second portion of the top surface of the substrate. An interconnect RF barrier is disposed between the RF circuitry and the semiconductor circuitry, the interconnect RF barrier coupled to a ground potential node.

    25.
    发明专利
    未知

    公开(公告)号：DE10301243B4

    公开(公告)日：2009-04-16

    申请号：DE10301243

    申请日：2003-01-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOLZ JUERGEN ,  BARTH HANS-JOACHIM

    IPC: H01L27/08 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/532

    Abstract: A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In the case of an electrically conductive hard mask, parts of the hard mask may remain in the circuit arrangement.

    26.
    发明专利
    未知

    公开(公告)号：DE102008046761A1

    公开(公告)日：2009-04-09

    申请号：DE102008046761

    申请日：2008-09-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BARTH HANS-JOACHIM ,  JETTEN HANS-GERD ,  TEWS HELMUT

    IPC: H01L23/538 ,  H01L21/441 ,  H01L21/822 ,  H01L23/532 ,  H01L27/08

    Abstract: The semiconductor structure (130) has a semiconductor chip (200) that is partially embedded within a support. An inductor (520) is electrically coupled to the semiconductor chip and portion of the inductor overlies in a magnetic region (300) which is outside the boundary of the semiconductor chip. An independent claim is included for manufacturing method of semiconductor structure.

    28.
    发明专利
    未知

    公开(公告)号：DE102005056907B3

    公开(公告)日：2007-08-16

    申请号：DE102005056907

    申请日：2005-11-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BARTH HANS-JOACHIM

    IPC: H01L25/065 ,  G11C5/06 ,  H01L23/34 ,  H01L23/488 ,  H01L23/498

    Abstract: A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips.

    30.
    发明专利
    未知

    公开(公告)号：DE10217876A1

    公开(公告)日：2003-11-06

    申请号：DE10217876

    申请日：2002-04-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BARTH HANS-JOACHIM ,  TEWS HELMUT

    IPC: C25D5/50 ,  C25D7/12 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768

    Abstract: The invention relates to a method for fabricating thin metal-containing layers ( 5 C) having low electrical resistance, firstly a metal-containing starting layer ( 5 A) having a first grain size being formed on a carrier material ( 2 ). Afterwards, a locally delimited thermal region (W) is produced and moved in the metal-containing starting layer ( 5 A) in such a way that a recrystallization of the metal-containing starting layer ( 5 A) is carried out for the purpose of producing the metal-containing layer ( 5 C) having a second grain size, which is enlarged with respect to the first grain size. A metal-containing layer having improved electrical properties is obtained in this way.

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