公开(公告)号：DE59814314D1

公开(公告)日：2008-12-11

申请号：DE59814314

申请日：1998-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  AEUGLE THOMAS ,  ROESNER WOLFGANG ,  RISCH LOTHAR

IPC: H01L29/78 ,  H01L21/336

Abstract: A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.

公开(公告)号：DE59914630D1

公开(公告)日：2008-03-13

申请号：DE59914630

申请日：1999-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  RAMCKE TIES ,  RISCH LOTHAR

IPC: H01L21/768 ,  H01L27/06 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/00 ,  H01L27/092 ,  H01L27/10 ,  H01L29/06 ,  H01L29/76

Abstract: At least one CMOS component which is configured in a semiconductor substrate is part of the inventive circuit assembly. An insulating layer is configured on the semiconductor substrate. The insulating layer covers the CMOS component. A nanoelectronic component is configured above the insulating layer. At least one conducting structure is configured in the insulating layer and serves to link the nanoelectronic component with the CMOS component. If several nanoelectronic components are provided, they are preferably grouped to nano-circuit blocks. Each of the nano-circuit blocks is so small that the RC times of their lines do not exceed 1 ns.

公开(公告)号：DE19935823B4

公开(公告)日：2006-07-13

申请号：DE19935823

申请日：1999-07-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  RISCH LOTHAR

IPC: H01L51/50 ,  C08L101/12 ,  H01L27/15 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56

公开(公告)号：DE10320239A1

公开(公告)日：2004-12-02

申请号：DE10320239

申请日：2003-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUVKEN JOHANNES ,  HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SPECHT MICHAEL ,  SCHLOESSER TILL ,  MANGER DIRK

IPC: H01L21/8238 ,  H01L21/8242 ,  H01L27/108

Abstract: A DRAM memory cell comprises a select transistor (200) on a semiconductor substrate with source/ drain electrodes (201,202), a channel layer (203), an isolated gate electrode, a memory capacitor (100) with two electrodes, one connected to the source/drain and a rear substrate electrode. The gate electrode surrounds opposite sides of the channel. An independent claim is also included for a production process for the above DRAM.

公开(公告)号：DE59902762D1

公开(公告)日：2002-10-24

申请号：DE59902762

申请日：1999-03-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  RAMCKE TIES ,  RISCH LOTHAR

IPC: G06F7/50 ,  G06F7/52 ,  H01L29/66 ,  H03K19/08

Abstract: The circuit configuration has at least five single-electron transistors, three of which are connected via a second main node and a third main node between a first main node and an output. The fourth single-electron transistor is connected between the second main node and a first supply voltage, with its gate electrode being connected to the first main node. The fifth single-electron transistor is connected between the third main node and the first supply voltage, with its gate electrode being connected to the second main node. The circuit configuration is suitable for use as a full adder and as a multiplier.

公开(公告)号：DE59804346D1

公开(公告)日：2002-07-11

申请号：DE59804346

申请日：1998-09-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RAMCKE TIES ,  ROESNER WOLFGANG ,  RISCH LOTHAR

IPC: G11C11/15 ,  G11C11/16 ,  G11C15/02 ,  G11C15/04 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A memory cell configuration has word lines and bit lines that extend transversely with respect thereto. Memory elements with a giant magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The bit lines are each connected to a sense amplifier by means of which the potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off. The memory cell configuration can be used both as an MRAM and as an associative memory.

公开(公告)号：DE59901323D1

公开(公告)日：2002-06-06

申请号：DE59901323

申请日：1999-01-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KRAUTSCHNEIDER WOLFGANG ,  RISCH LOTHAR ,  HOFMANN FRANZ ,  ROESNER WOLFGANG

IPC: H01L21/8242 ,  H01L27/108

Abstract: The memory cell has a capacitor electrode (Sk), provided at its flanks with a capacitor dielectric (Kd), with the bit line (B2) coupled to the storage capacitor (Ko) acting as the second capacitor electrode. The first capacitor electrode is surrounded in a ring by the capacitor dielectric, with a selection transistor positioned beneath the capacitor and connected to the first capacitor electrode. The transistor may be positioned between the capacitor and a second bit line.

公开(公告)号：DE19928564A1

公开(公告)日：2001-01-04

申请号：DE19928564

申请日：1999-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  RISCH LOTHAR ,  FRANOSCH MARTIN

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/788

Abstract: A dual-gate MOSFET semiconductor layer structure is constructed on a substrate (1). Said semiconductor layer structure consists of a first gate electrode and a second gate electrode (10A, 10B), between which a semiconductor channel layer area (4A) is embedded, and a source area (2A) and a drain area (2B), which are situated on opposite front sides of the semiconductor channel layer area (4A). At least one other semiconductor channel layer area (6A) is provided at one of the gate electrodes (10B), the front sides of this semiconductor channel layer area (6A) also being contacted by the source (2A) and drain (2B) areas.

公开(公告)号：DE59813900D1

公开(公告)日：2007-03-22

申请号：DE59813900

申请日：1998-08-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  RAMCKE TIES ,  RISCH LOTHAR

IPC: G06F7/501 ,  H01L29/76 ,  G06F7/50 ,  G06F7/505 ,  H01L29/66 ,  H03K17/00 ,  H03K19/02

Abstract: At least one single-electron transistor is provided in a circuit configuration having single-electron components, and is connected between a first main node and a second main node. The first main node is capacitively connected between a first operating voltage connection and a second operating voltage connection. The gate electrode of the single-electron transistor is connected to a control voltage connection. The circuit configuration is suitable for logic operations on binary numbers, whose digits are stored at the first and second main nodes.

公开(公告)号：DE50013984D1

公开(公告)日：2007-03-08

申请号：DE50013984

申请日：2000-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SCHLOESSER TILL

IPC: H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: The invention relates to a transistor that is provided with a first source/drain area (S/D 1 ), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2 ) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D 1 ). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D 1 ) are arranged in the insulating area. The second source/drain area (S/D 2 ) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.