公开(公告)号：DE10211932B9

公开(公告)日：2006-03-30

申请号：DE10211932

申请日：2002-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS

IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/00 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50 ,  H03F3/195

Abstract: A circuit arrangement includes a bit line ( 10 ), a reference bit line ( 12 ), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor ( 20, 22 ) and a p-channel field-effect transistor ( 30, 32 ), and also, at the respective source terminals, two voltage sources ( 40, 42 ), of which the voltage source ( 40 ) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source ( 42 ) linked to the p-channel field-effect transistors ( 30, 32 ) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell ( 4 ) on the bit line ( 10 ) if the threshold voltages (U TH1 , U TH2 ) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell ( 4 ).

公开(公告)号：DE10211932B4

公开(公告)日：2005-09-15

申请号：DE10211932

申请日：2002-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS

IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50 ,  G11C29/00 ,  H03F3/195

Abstract: A circuit arrangement includes a bit line ( 10 ), a reference bit line ( 12 ), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor ( 20, 22 ) and a p-channel field-effect transistor ( 30, 32 ), and also, at the respective source terminals, two voltage sources ( 40, 42 ), of which the voltage source ( 40 ) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source ( 42 ) linked to the p-channel field-effect transistors ( 30, 32 ) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell ( 4 ) on the bit line ( 10 ) if the threshold voltages (U TH1 , U TH2 ) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell ( 4 ).

公开(公告)号：DE10131675B4

公开(公告)日：2005-04-07

申请号：DE10131675

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LINDOLF JUERGEN ,  POPP MARTIN ,  SELL BERNHARD

IPC: G01R27/26 ,  G11C29/50 ,  G11C29/00 ,  G01R31/26 ,  G11C11/4076

Abstract: A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its associated lead resistor, is coupled to the interconnect either via an interconnect or a transistor can selectively coupled and decouple the capacitor and the lead resistance. A measuring device is connected up to the ring oscillator and is used to determine a value for the oscillation frequency of the ring oscillator on the basis of which a value for the time constant of the storage capacitor can be determined.

公开(公告)号：DE10208450A1

公开(公告)日：2003-09-11

申请号：DE10208450

申请日：2002-02-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAENGER ANNETTE ,  SELL BERNHARD ,  SEIDL HARALD ,  HECHT THOMAS ,  GUTSCHE MARTIN

IPC: C23C16/34 ,  C23C16/40 ,  C23C16/42 ,  C23C16/44 ,  C23C16/455 ,  C23C16/46 ,  C23C16/48 ,  C23C16/30

Abstract: Process chamber for producing a layer of material on sections of a surface (8) of a substrate (3) comprises: holding unit (2) for substrate; feeding and removal units (6) for gas phases of chemical precursors of the layer material; substrate feeding device (11) for introducing substrate into process chamber; heating source (9) for heating the substrate and/or substrate surface; and control unit. The control unit is used for sequentially introducing the chemical precursor compounds. The heating source (9) is formed as a radiation source, by means of which the temperature on the substrate surface can be changed in steps of more than 100 K per second. The radiation source is a heating lamp and is arranged in the chamber inner chamber (5) of the process chamber enclosed by a chamber wall (4). An Independent claim is also included for a process for depositing a layer of material on sections of a surface of a substrate.

公开(公告)号：DE10203998A1

公开(公告)日：2003-08-21

申请号：DE10203998

申请日：2002-02-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LANDGRAF ERHARD ,  SELL BERNHARD ,  HOFMANN FRANZ ,  LUYKEN R JOHANNES ,  GOLDBACH MATTHIAS

IPC: B81C1/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423 ,  H01L21/336 ,  H01L21/8247

Abstract: Production of a toothed structure in a crystal structure in or on a substrate (100) comprises forming trenches (102, 202) using a mask on the substrate and an etching process, and etching the unmasked region of the substrate having at least one trench to form the toothed structure. Independent claims are also included for: method for producing a floating gate transistor; and floating gate transistor. Preferred Features: The crystal structure contains silicon. The structured surface of the crystal structure in the substrate has a (100) crystal orientation according to the Miller Indices. The trench is trapezoidal or V-shaped. A silicon dioxide layer is applied to the toothed structure.

公开(公告)号：DE10134461A1

公开(公告)日：2003-02-06

申请号：DE10134461

申请日：2001-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHULZE-ICKING GEORG

IPC: H01L21/285 ,  H01L21/768 ,  C23C16/42 ,  H01L21/8242

公开(公告)号：DE10131675A1

公开(公告)日：2003-01-16

申请号：DE10131675

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LINDOLF JUERGEN ,  POPP MARTIN ,  SELL BERNHARD

IPC: G01R27/26 ,  G11C29/50 ,  G11C11/4076

Abstract: A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its associated lead resistor, is coupled to the interconnect either via an interconnect or a transistor can selectively coupled and decouple the capacitor and the lead resistance. A measuring device is connected up to the ring oscillator and is used to determine a value for the oscillation frequency of the ring oscillator on the basis of which a value for the time constant of the storage capacitor can be determined.

公开(公告)号：DE10128481A1

公开(公告)日：2003-01-02

申请号：DE10128481

申请日：2001-06-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  SELL BERNHARD ,  HECHT THOMAS

IPC: B44C1/22 ,  C03C25/68 ,  G03F7/26 ,  H01L21/308 ,  H01L21/31

Abstract: An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.

公开(公告)号：DE10109328A1

公开(公告)日：2002-09-12

申请号：DE10109328

申请日：2001-02-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  THIEME PETER ,  DRUMMER HEIKE

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3213

Abstract: The invention relates to a semiconductor substrate (1) on which a first layer (2), a second layer (3) and a third layer (4) are disposed. The third layer (4) is for example a lacquer mask that is used to structure the second layer (3). The second layer (3) is for example a structured hard mask that is used to structure the first layer (2). The third layer (4) is then removed and a fourth layer (8) is deposited. The fourth layer (8) is for example an insulator that fills the trenches formed in the first layer (2). The fourth layer (8) is then planarized in a CMP step, and planarization is continued while the second layer (3) that is for example a hard mask is removed from the first layer (2) together with the fourth layer (8), thereby leaving the fourth layer (8) in a trench (7) that is disposed in the first layer (2).

公开(公告)号：DE10109218A1

公开(公告)日：2002-06-27

申请号：DE10109218

申请日：2001-02-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

Abstract: Production of a storage capacitor comprises forming a lower metallic capacitor electrode (13), a storage dielectric (14) and an upper capacitor electrode (15). The lower capacitor electrode is formed on a silicon base material (1) in a self-adjusting manner so that exposed silicon regions are formed. A metal silicide is then selectively formed on the exposed regions. Preferred Features: The metal is W, Ti, Mo, Ta, Co, Ni, Pt, Pd or a rare earth. The step of selectively forming a metal silicide on the exposed silicon regions comprises depositing a metal (12), heat treating at a prescribed temperature, and selectively removing unreacted metal. The heat treatment step is carried out at 600-1000 deg C in a nitrogen atmosphere.