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    Functional unit for vector integer multiply add instruction
    21.
    发明专利
    Functional unit for vector integer multiply add instruction 未知

    公开(公告)号：GB2497450A

    公开(公告)日：2013-06-12

    申请号：GB201303473

    申请日：2011-09-23

    Applicant: INTEL CORP

    Inventor： WIEDEMEIER JEFF ,  SAMUDRALA SRIDHAR ,  GOLLIVER ROGER A

    IPC: G06F9/30 ,  G06F7/483

    Abstract: A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation.

    Controlling access to multiple isolated memories in an isolated execution environment
    24.
    发明专利
    Controlling access to multiple isolated memories in an isolated execution environment 未知

    公开(公告)号：GB2381626A

    公开(公告)日：2003-05-07

    申请号：GB0303644

    申请日：2001-07-13

    Applicant: INTEL CORP

    Inventor： GOLLIVER ROGER A ,  SUTTON JAMES II ,  LIN DERRICK ,  THAKKAR SHREEKANT ,  NEIGER GILBERT ,  MCKEEN FRANCIS ,  HERBERT HOWARD ,  RENERIS KENNETH ,  ELLISON CARL

    IPC: G06F12/14

    Abstract: The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is divided into non-isolated areas and isolated areas. The page manager is located in an isolated area of memory. Further, a memory ownership page table describes each page of memory and is also located in an isolated area of memory. The page manager assigns an isolated attribute to a page if the page is distributed to an isolated are of memory. On the other hand, the page manager assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory. The memory ownership page table records the attribute for each page. In one embodiment, a processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that contains configuration settings related to a page and access information. An access checking circuit coupled to the configuration settings and the access information and generates an access grant signal if the access transaction is valid.

    27.
    发明专利
    未知

    公开(公告)号：DE19983870T1

    公开(公告)日：2002-04-11

    申请号：DE19983870

    申请日：1999-12-08

    Applicant: INTEL CORP

    Inventor： MAKINENI SIVAKUMAR ,  KIMN SNNHYUK ,  DOSHI GAUTMAN B ,  GOLLIVER ROGER A

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318

    Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

    Computation of implicit data type bits for SIMD operations
    29.
    发明专利
    Computation of implicit data type bits for SIMD operations 未知

    公开(公告)号：GB2360110A

    公开(公告)日：2001-09-12

    申请号：GB0114436

    申请日：1999-12-08

    Applicant: INTEL CORP

    Inventor： MAKINENI SIVAKUMAR ,  KIMN SNNHYUK ,  DOSHI GAUTMAN B ,  GOLLIVER ROGER A

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318

    Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

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