公开(公告)号：GB2287108A

公开(公告)日：1995-09-06

申请号：GB9416585

申请日：1994-08-17

Applicant: INTEL CORP

Inventor： COLWELL ROBERT P ,  FETTERMAN MICHAEL ALAN ,  GLEW ANDREW F ,  HINTON GLENN J ,  MARTELL ROBERT W ,  PAPWORTH DAVID B

IPC: G06F9/38 ,  G06F9/28

公开(公告)号：DE112013003255T5

公开(公告)日：2015-05-13

申请号：DE112013003255

申请日：2013-06-03

Applicant: INTEL CORP

Inventor： RAMANUJAN RAJ K ,  HINTON GLENN J ,  ZIMMERMANN DAVID J

IPC: G06F11/00 ,  G06F11/07 ,  G11C29/00

Abstract: Ein System schließt ein nicht flüchtiger Random Access Memory-(NVRAM)-Gerät und Steuerlogik ein, die einen fehlerhaften Block innerhalb des Gerätes erkennt, den fehlerhaften Block rückordnet und den fehlerhaften Block mit einem Ersatzblock durch Zuordnen der Adresse des fehlerhaften Blocks zum Ersatzblock ersetzt.

公开(公告)号：DE102014003399A1

公开(公告)日：2014-09-18

申请号：DE102014003399

申请日：2014-03-07

Applicant: INTEL CORP

Inventor： RASH WILLIAM C ,  HAHN SCOTT D ,  TOLL BRET L ,  HINTON GLENN J

IPC: G06F9/38

Abstract: Systeme und Verfahren zur Implementierung transaktionalen Speicherzugriffs Ein beispielhaftes Verfahren kann das Initialisieren einer Speicherzugriffstransaktion, Ausführen einer transaktionalen Leseoperation hinsichtlich einer ersten Speicherstelle unter Verwendung eines ersten, mit einer Speicherzugriffsverfolgungslogik assoziierten Puffers, und/oder einer transaktionalen Schreiboperation hinsichtlich einer zweiten Speicherstelle unter Verwendung eines zweiten, mit der Speicherzugriffsverfolgungslogik assoziierten Puffers, Ausführen einer nicht-transaktionalen Leseoperation hinsichtlich einer dritten Speicherstelle, und/oder einer nicht-transaktionalen Schreiboperation hinsichtlich einer vierten Schreibstelle, Abbrechen der Speicherzugriffstransaktion als Reaktion auf das Erkennen durch die Speicherzugriffsverfolgungslogik eines Zugriffs eines anderen als der Prozessor Geräts auf die erste Speicherstelle oder die zweite Speicherstelle, und Abschließen der Speicherzugriffstransaktion unabhängig von dem Status der dritten Speicherstelle und der vierten Speicherstelle als Reaktion auf das Nicht-Erkennen einer Transaktionsabbruchbedingung, umfassen.

公开(公告)号：GB2469373A

公开(公告)日：2010-10-13

申请号：GB201005305

申请日：2010-03-29

Applicant: INTEL CORP

Inventor： TRIKA SANJEEV N ,  HUFFMAN AMBER D ,  BOYD JAMES A ,  HADY FRANK T ,  HINTON GLENN J ,  JUENEMANN DALE J ,  PINTO OSCAR P ,  TETRICK SCOTT R ,  BARNES THOMAS J ,  BURRIDGE SCOTT E

IPC: G06F12/08

Abstract: A computer system has a storage medium, such as a hard disc drive, on which to store data. The data is cached in another memory. The cache memory may be NAND flash. Data may be evicted from the cache when a file is deleted, when a file is replaced by another with the same name or when a file is moved to a device, which is not cached. The address of data in the cache may be changed if the operating system moves the data. Data associated with a file may be cached when the file is opened. The system may not cache data for streamed files. There may be a list of file types or file extensions, which are not cached. There may be a list of file types or extensions, which are not evicted. Data accessed by a mining operation may not be cached.

公开(公告)号：DE4447238B4

公开(公告)日：2005-08-18

申请号：DE4447238

申请日：1994-12-30

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38 ,  G06F9/28

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：DE10085438T1

公开(公告)日：2003-01-16

申请号：DE10085438

申请日：2000-12-29

Applicant: INTEL CORP

Inventor： UPTON MICHAEL ,  SAGER DAVID A ,  BOGGS DARRELL D ,  HINTON GLENN J

IPC: G06F9/38

Abstract: According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.

公开(公告)号：AU2464001A

公开(公告)日：2001-08-27

申请号：AU2464001

申请日：2000-12-29

Applicant: INTEL CORP

Inventor： UPTON MICHAEL D ,  SAGER DAVID A ,  BOGGS DARRELL D ,  HINTON GLENN J

IPC: G06F9/38

Abstract: According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.

公开(公告)号：DK0661625T3

公开(公告)日：2000-04-03

申请号：DK94307771

申请日：1994-10-21

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38

Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

公开(公告)号：ES2138051T3

公开(公告)日：2000-01-01

申请号：ES94307771

申请日：1994-10-21

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN

IPC: G06F9/38

Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

公开(公告)号：DE69420540D1

公开(公告)日：1999-10-14

申请号：DE69420540

申请日：1994-10-21

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38

Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.