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    A system for providing the absolute difference of unsigned values
    21.
    发明专利
    A system for providing the absolute difference of unsigned values 未知

    公开(公告)号：AU1426397A

    公开(公告)日：1997-07-17

    申请号：AU1426397

    申请日：1996-12-18

    Applicant: INTEL CORP

    Inventor： MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  GOTTLIEB KOBY

    IPC: G06F7/544 ,  G06F9/302 ,  G06F7/50 ,  G06F9/30

    Abstract: In a computer system storing a first packed data and a second packed data having corresponding data elements where the data elements representing unsigned values having a system for determining the absolute difference of the corresponding data elements. The system comprising the steps of subtracting with saturation the data elements in the first packed data from the corresponding data elements in the second packed data to generate a third packed data in response to a first instruction, subtracting with saturation the data elements in the second packed data from the corresponding data elements in the first packed data to generate a fourth packed data in response to a second instruction and performing an operation to select the data elements of the third packed data and the fourth packed data of greatest value to generate a fifth packed data in response to a third instruction.

    A method of performing different data type operations that is invisible to various operating system techniques
    22.
    发明专利
    A method of performing different data type operations that is invisible to various operating system techniques 未知

    公开(公告)号：AU1430597A

    公开(公告)日：1997-07-14

    申请号：AU1430597

    申请日：1996-12-17

    Applicant: INTEL CORP

    Inventor： GLEW ANDREW F ,  VAKKALAGADDA RAMAMOHAN R ,  LIN DERRICK ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI EIICHI ,  EITAN BENNY

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/455 ,  G06F9/46 ,  G06F9/34 ,  G06F9/00 ,  G06F9/302

    Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.

    AN APPARATUS FOR CONTROLLING BIT CORRECTION OF SHIFTED PACKED DATA
    25.
    发明专利
    AN APPARATUS FOR CONTROLLING BIT CORRECTION OF SHIFTED PACKED DATA 未知

    公开(公告)号：HK1144974A1

    公开(公告)日：2011-03-18

    申请号：HK10111583

    申请日：2010-12-13

    Applicant: INTEL CORP

    Inventor： PELEG ALEXANDER D ,  YAARI YAAKOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

    IPC: G06F20060101 ,  G06F5/00 ,  G06F7/544 ,  G06F7/57 ,  G06F7/60 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78

    Abstract: An apparatus comprising: a first storage area operable to have stored therein a first packed data containing at least an A 1 , an A 2 , an A 3 , and an A 4 element; a second storage area operable to have stored therein a second packed data containing at least a B 1 , a B 2 , a B 3 , and a B 4 element; a multiply circuit including a first multiplier coupled to said first storage area to receive said A 1 and coupled to said second storage area to receive said B 1 ; a second multiplier coupled to said first storage area to receive said A 2 and coupled to said second storage are to receive said B 2 ; a third multiplier coupled to said first storage area to receive said A 3 and coupled to said second storage area to receive said B 3 ; a fourth multiplier coupled to said first storage area to receive said A 4 and coupled to said second storage area to receive said B 4 ; a first adder coupled to said first multiplier and said second multiplier; a second adder coupled to said third multiplier and said fourth multiplier; and a third storage area coupled to said first adder and said second adder, said third storage area having at least a first field and a second field, said first field for saving an output of said first adder as a first data element of a third packed data, said second field for saving an output of said second adder as a second data element of said third packed data.

    MANIPULATING VIDEO AND AUDIO SIGNALS USING A PROCESSOR WHICH SUPPORTS SIMD INSTRUCTIONS
    29.
    发明专利
    MANIPULATING VIDEO AND AUDIO SIGNALS USING A PROCESSOR WHICH SUPPORTS SIMD INSTRUCTIONS 未知

    公开(公告)号：HK1015486A1

    公开(公告)日：1999-10-15

    申请号：HK99100506

    申请日：1999-02-05

    Applicant: INTEL CORP

    Inventor： DULONG CAROLE ,  PELEG ALEXANDER D ,  MENNEMEIER LARRY M

    IPC: G06T1/20 ,  G06F ,  H04N

    Abstract: A computer system which manipulates audio and video signals. A multimedia input device which generates an audio and/or video signal is coupled to a processor. The processor is also coupled to a storage device upon which a decompression routine is stored, the decompression routine including a transposition routine. The transposition routine manipulates data elements associated with the audio or video signal in transposing an array of n rows of a plurality of data elements. The transposition routine causes the processor to interleave data elements from a first row with data elements from a second row to generate a first result. Data elements from a third row are interleaved with data elements from a fourth row to generate a second result. Then, data elements from the first result are interleaved with data elements from the second result to generate a third result.\!

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