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    TECHNIQUES FOR IMPROVING MSAA RENDERING EFFICIENCY
    22.
    发明公开
    TECHNIQUES FOR IMPROVING MSAA RENDERING EFFICIENCY 审中-公开
    一种提高MSSA的效率

    公开(公告)号：EP2936440A4

    公开(公告)日：2016-09-21

    申请号：EP13868697

    申请日：2013-12-19

    Applicant: INTEL CORP

    Inventor： SURTI PRASOONKUMAR ,  PIAZZA THOMAS A

    IPC: G06T15/00 ,  G06T1/20

    CPC classification number: G06T15/503 ,  G06T11/40 ,  G06T15/005 ,  G06T2200/12 ,  G06T2210/08

    Abstract: Various embodiments are generally directed to techniques for causing the storage of a color data value of a clear color to be deferred as rendered color data values are stored for samples. A device comprises a processor circuit and a storage to store instructions that cause the processor circuit to render a pixel from multiple samples taken of a three-dimensional model of an object, the pixel corresponding to a pixel sample data which comprises multiple color storage locations that are each identified by a numeric identifier, and which comprises multiple sample color indices that each correspond to a sample to point to at least one color storage location; and allocate color storage locations in an order selected to define a subset of possible combinations of binary index values among all of the sample color indices as invalid combinations. Other embodiments are described and claimed.

    Cache coherency between a CPU cache hierarchy and a graphics cache hierarchy
    29.
    发明专利
    Cache coherency between a CPU cache hierarchy and a graphics cache hierarchy 未知

    公开(公告)号：GB2495032A

    公开(公告)日：2013-03-27

    申请号：GB201222945

    申请日：2009-03-27

    Applicant: INTEL CORP

    Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

    IPC: G06F12/08

    Abstract: A processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. A graphics device 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The processor has a level 1 processor cache 103 (L1 cache) and a lower level processor cache 107. The graphics device has a level 1 graphics cache 104 (L1 cache) and a lower level graphics cache 108. The central processing unit uses the first set of coherency rules with the lower level graphics cache. The graphics device uses the second set of coherency rules with the lower level graphics cache. The lower level graphics cache may be a mid-level or last level cache. The processor may snoop the lower level graphics cache.

    Cache coherency between a CPU cache hierarchy and a graphics cache hierarchy
    30.
    发明专利
    Cache coherency between a CPU cache hierarchy and a graphics cache hierarchy 未知

    公开(公告)号：GB2490821A

    公开(公告)日：2012-11-14

    申请号：GB201214187

    申请日：2009-03-27

    Applicant: INTEL CORP

    Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

    IPC: G06F12/08

    Abstract: A processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. A graphics device 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The processor has a level 1 processor cache 103 (L1 cache) and a lower level processor cache 107. The graphics device has a level 1 graphics cache 104 (L1 cache) and a lower level graphics cache 108. The central processing unit uses the first set of coherency rules with the lower level graphics cache. The graphics device uses the second set of coherency rules with the lower level graphics cache. The lower level graphics cache may be a mid-level or last level cache. The processor may snoop the lower level graphics cache.

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