公开(公告)号：GB2493880A

公开(公告)日：2013-02-20

申请号：GB201221421

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A first processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. Another processor 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The first processor has a level 1 processor cache 103 (L1 cache) and a lower level processor cache 107. The second processor has a level 1 graphics cache 104 (L1 cache) and a lower level cache 108. The first processor uses the first set of coherency rules with the lower level graphics cache. The second processor uses the second set of coherency rules with the lower level graphics cache. The lower level graphics cache may be a mid-level or last level cache. The first processor may snoop the lower level graphics cache.

公开(公告)号：DE112009000373T5

公开(公告)日：2011-01-27

申请号：DE112009000373

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ALTUG ,  KAHN OPER

IPC: G06F12/00 ,  G06F9/00 ,  G06T1/00 ,  H04L12/00

公开(公告)号：WO2009120997A3

公开(公告)日：2009-12-30

申请号：PCT/US2009038627

申请日：2009-03-27

Applicant: INTEL CORP ,  OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ALTUG ,  KAHN OPER

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ALTUG ,  KAHN OPER

IPC: G06F12/00 ,  G06F9/00 ,  G06T1/00 ,  H04L12/00

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0828 ,  G06F12/0835 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4282 ,  G06F2212/283 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2213/0026 ,  G06T1/60 ,  G11C7/1072

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract translation: 一种技术，可以在不同缓存一致性域内的代理之间共享信息。 在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，该信息可以由一个或多个处理核心以不影响与该处理核心有关的编程和一致性规则的方式 图形设备。

公开(公告)号：GB2487328B

公开(公告)日：2012-10-03

申请号：GB201207247

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ALTUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：GB2471786B

公开(公告)日：2012-09-05

申请号：GB201015007

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ALTUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：DE112009005503A5

公开(公告)日：2013-07-11

申请号：DE112009005503

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： FARRELL ROBERT L ,  BERKOVITS ARIEL ,  KOKER ALTUG ,  OFFEN ZEEV ,  KAHN OPER ,  PIAZZA THOMAS A

IPC: G06F12/08 ,  G06F9/00 ,  G06T1/00 ,  H04L12/00

公开(公告)号：GB2495032B

公开(公告)日：2013-05-08

申请号：GB201222945

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：GB2493880B

公开(公告)日：2013-03-27

申请号：GB201221421

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：GB2490821B

公开(公告)日：2013-01-30

申请号：GB201214187

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：GB2495032A

公开(公告)日：2013-03-27

申请号：GB201222945

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. A graphics device 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The processor has a level 1 processor cache 103 (L1 cache) and a lower level processor cache 107. The graphics device has a level 1 graphics cache 104 (L1 cache) and a lower level graphics cache 108. The central processing unit uses the first set of coherency rules with the lower level graphics cache. The graphics device uses the second set of coherency rules with the lower level graphics cache. The lower level graphics cache may be a mid-level or last level cache. The processor may snoop the lower level graphics cache.