中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

32 records (took 0.02 seconds)

    BEHAVIORAL MODEL BASED MULTI-THREADED ARCHITECTURE
    1.
    发明申请
    BEHAVIORAL MODEL BASED MULTI-THREADED ARCHITECTURE 审中-公开
    基于行为模型的多层建筑

    公开(公告)号：WO2005066768A3

    公开(公告)日：2007-02-22

    申请号：PCT/US2004043395

    申请日：2004-12-23

    Applicant: INTEL CORP ,  JIANG HONG ,  PIAZZA THOMAS A

    Inventor： JIANG HONG ,  PIAZZA THOMAS A

    IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48

    CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/4843

    Abstract: Multiple parallel passive threads of instructions coordinate access to shared resources using "active" and "proactive" semaphores. The active semaphores send messages to execution and/or control circuitry to cause the state of a thread to change. A thread can be placed in an inactive state by a thread scheduler in response to an unresolved dependency, which can be indicated by a semaphore. A thread state variable corresponding to the dependency is used to indicate that the thread is in inactive mode. When the dependency is resolved a message is passed to control circuitry causing the dependency variable to be cleared. In response to the cleared dependency variable the thread is placed in an active state. Execution can proceed on the threads in the active state. A proactive semaphore operates in a similar manner except that the semaphore is configured by the thread dispatcher before or after the thread is dispatched to the execution circuitry for execution.

    Abstract translation: 指令的多个并行被动线程使用“主动”和“主动”信号量协调对共享资源的访问。 主动信号量将消息发送到执行和/或控制电路，以使线程的状态发生变化。 线程调度程序可以响应未解决的依赖关系将线程置于无效状态，这可以由信号量指示。 与依赖关系对应的线程状态变量用于指示线程处于非活动模式。 当依赖关系被解析时，消息被传递给控制电路，导致依赖变量被清除。 响应于清除的依赖变量，线程处于活动状态。 处于活动状态的线程可执行。 主动信号量以类似的方式运行，除了信号量由线程分派器在线程发送到执行电路执行之前或之后配置。

    METHOD AND APPARATUS FOR ARBITRATION IN A UNIFIED MEMORY ARCHITECTURE
    3.
    发明申请
    METHOD AND APPARATUS FOR ARBITRATION IN A UNIFIED MEMORY ARCHITECTURE 审中-公开
    在统一的存储器架构中进行仲裁的方法和装置

    公开(公告)号：WO0041083A3

    公开(公告)日：2002-05-16

    申请号：PCT/US9930719

    申请日：1999-12-21

    Applicant: INTEL CORP ,  CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

    Inventor： CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

    IPC: G06F12/00 ,  G06F12/02 ,  G06F13/18 ,  G06F13/362

    CPC classification number: G06F13/18

    Abstract: According to one embodiment, a computer system is disclosed that includes a memory and a memory controller coupled to the memory. The memory controller includes an arbitration unit that may be programmed to operate according to a first arbitration mode or a second arbitration mode. The computer system also includes a first device and a second device coupled to the arbitration unit. According to a further embodiment, the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode. In addition, the first device and the second device are assigned equal priority classifications for accessing the memory while the arbitration unit is operating according to the second arbitration mode.

    Abstract translation: 根据一个实施例，公开了一种包括存储器和耦合到存储器的存储器控​​制器的计算机系统。 存储器控制器包括可被编程为根据第一仲裁模式或第二仲裁模式进行操作的仲裁单元。 计算机系统还包括耦合到仲裁单元的第一设备和第二设备。 根据另一实施例，当仲裁单元根据第一仲裁模式操作时，第一设备被分配比用于访问存储器的第二设备更高的优先级分类。 此外，当仲裁单元根据第二仲裁模式操作时，第一设备和第二设备被分配用于访问存储器的相同的优先级分类。

    THREAD QUEUING METHOD AND APPARATUS
    6.
    发明公开
    THREAD QUEUING METHOD AND APPARATUS 审中-公开
    VERFAHREN UND VORRICHTUNGFÜRTHREADREIHUNG

    公开(公告)号：EP2097814A4

    公开(公告)日：2010-09-01

    申请号：EP07869461

    申请日：2007-12-18

    Applicant: INTEL CORP

    Inventor： JIANG HONG ,  PIAZZA THOMAS A ,  RAUCHFUSS BRIAN D ,  CHALASANI SREEDEVI ,  SPANGLER STEVEN J

    IPC: G06F9/46

    CPC classification number: G06F9/546

    Abstract: In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include fetching a plurality of instructions in response at least in part to the request supplied to the queue and executing at least one of the plurality of instructions. In some embodiments, an apparatus includes a storage medium having stored therein instructions that when executed by a machine result in the method. In some embodiments, an apparatus includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request. In some embodiments, a system includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request, and a memory unit to store at least one instruction for the thread.

    Abstract translation: 在一些实施例中，一种方法包括接收生成线程的请求并至少响应于接收的请求向队列提供请求。 该方法还可以包括至少部分地响应于提供给队列的请求并且执行多个指令中的至少一个指令来获取多个指令。 在一些实施例中，一种装置包括存储介质，其中存储有当机器执行时产生该方法的指令。 在一些实施例中，装置包括用于接收生成线程的请求并至少对所接收的请求作出响应来排队请求生成线程的电路。 在一些实施例中，系统包括电路，用于接收生成线程的请求，并至少响应于所接收的请求来对请求进行排队以生成线程;以及存储器单元，用于存储线程的至少一条指令。

    Cache coherency between CPU cache hierarchies
    7.
    发明专利
    Cache coherency between CPU cache hierarchies 未知

    公开(公告)号：GB2493880A

    公开(公告)日：2013-02-20

    申请号：GB201221421

    申请日：2009-03-27

    Applicant: INTEL CORP

    Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

    IPC: G06F12/08

    Abstract: A first processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. Another processor 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The first processor has a level 1 processor cache 103 (L1 cache) and a lower level processor cache 107. The second processor has a level 1 graphics cache 104 (L1 cache) and a lower level cache 108. The first processor uses the first set of coherency rules with the lower level graphics cache. The second processor uses the second set of coherency rules with the lower level graphics cache. The lower level graphics cache may be a mid-level or last level cache. The first processor may snoop the lower level graphics cache.

Patent Agency Ranking