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公开(公告)号：GB2493880A
公开(公告)日：2013-02-20
申请号：GB201221421
申请日：2009-03-27
Applicant: INTEL CORP
Inventor： OFFEN ZEEV , BERKOVITS ARIEL , PIAZZA THOMAS A , FARRELL ROBERT L , KOKER ATLUG , KAHN OPER
IPC: G06F12/08
Abstract: A first processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. Another processor 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The first processor has a level 1 processor cache 103 (L1 cache) and a lower level processor cache 107. The second processor has a level 1 graphics cache 104 (L1 cache) and a lower level cache 108. The first processor uses the first set of coherency rules with the lower level graphics cache. The second processor uses the second set of coherency rules with the lower level graphics cache. The lower level graphics cache may be a mid-level or last level cache. The first processor may snoop the lower level graphics cache.
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公开(公告)号：WO03096170A2
公开(公告)日：2003-11-20
申请号：PCT/US0310428
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： CUI YING , SAMSON ERIC , BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY
CPC classification number: G06F1/3228 , G06F1/3215 , G06F1/324 , G06F1/325 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
Abstract translation: 在本发明的一个实施例中，描述了一种集成装置，其采用机制来通过从时钟发生器接收的时钟信号的电压和频率调整来控制图形存储器控制器集线器（GMCH）的功率消耗。 GMCH包括图形核心和改变操作行为的电路，例如提供给图形核心的渲染时钟信号的频率。 该电路适用于监视图形核心的空闲，并且如果闲置时间超过确定的时间百分比，则降低渲染时钟信号的频率水平。
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3.发明申请
公开(公告)号：WO2009120997A3
公开(公告)日：2009-12-30
申请号：PCT/US2009038627
申请日：2009-03-27
Applicant: INTEL CORP , OFFEN ZEEV , BERKOVITS ARIEL , PIAZZA THOMAS A , FARRELL ROBERT L , KOKER ALTUG , KAHN OPER
Inventor： OFFEN ZEEV , BERKOVITS ARIEL , PIAZZA THOMAS A , FARRELL ROBERT L , KOKER ALTUG , KAHN OPER
CPC classification number: G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
Abstract translation: 一种技术，可以在不同缓存一致性域内的代理之间共享信息。 在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，该信息可以由一个或多个处理核心以不影响与该处理核心有关的编程和一致性规则的方式 图形设备。
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公开(公告)号：DE112009000373T5
公开(公告)日：2011-01-27
申请号：DE112009000373
申请日：2009-03-27
Applicant: INTEL CORP
Inventor： OFFEN ZEEV , BERKOVITS ARIEL , PIAZZA THOMAS A , FARRELL ROBERT L , KOKER ALTUG , KAHN OPER
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公开(公告)号：GB2405009B
公开(公告)日：2005-08-24
申请号：GB0424629
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： CUI YING , SAMSON ERIC , BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE E , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
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Patent Agency Ranking
公开(公告)号：GB2405009A
公开(公告)日：2005-02-16
申请号：GB0424629
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： CUI YING , SAMSON ERIC , BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE E , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) (140) through both voltage and frequency adjustment of clock signal received from a clock generator (120). The GMCH (140) comprises a graphics core (200) and a circuit (235) to alter operational behavior, such as the frequency of a render clock signal (270) supplied to the graphics core (200). The circuit (235) is adapted to monitor idleness of the graphics core (200) and reduce a frequency level of the render clock (270) signal if the idleness exceeds a determined percentage of time.
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公开(公告)号：AU2003223464A1
公开(公告)日：2003-11-11
申请号：AU2003223464
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY , CUI YING , SAMSON ERIC
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
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公开(公告)号：GB2487328B
公开(公告)日：2012-10-03
申请号：GB201207247
申请日：2009-03-27
Applicant: INTEL CORP
Inventor： OFFEN ZEEV , BERKOVITS ARIEL , PIAZZA THOMAS A , FARRELL ROBERT L , KOKER ALTUG , KAHN OPER
IPC: G06F12/08
Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
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公开(公告)号：GB2471786B
公开(公告)日：2012-09-05
申请号：GB201015007
申请日：2009-03-27
Applicant: INTEL CORP
Inventor： OFFEN ZEEV , BERKOVITS ARIEL , PIAZZA THOMAS A , FARRELL ROBERT L , KOKER ALTUG , KAHN OPER
IPC: G06F12/08
Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
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公开(公告)号：DE10392619B4
公开(公告)日：2008-10-16
申请号：DE10392619
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： CUI YING , SAMSON ERIC , BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
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