公开(公告)号：GB2398141A

公开(公告)日：2004-08-11

申请号：GB0407203

申请日：2002-08-30

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/45 ,  G06F9/38

Abstract: A method and apparatus for providing compiler transformation of code using regions with simplified data and control flow and value specialization are described. In one embodiment, the method includes identifying in the code a plurality of potential candidates for value specialization, selecting a group of candidates from the plurality of potential candidates based on a value profile associated with each potential candidate, and determining specialized data for each selected candidate using a corresponding value profile. The method further includes forming a plurality of optimized regions based on corresponding specialized data. Each optimized region includes one or more selected candidates.

公开(公告)号：EP3234766A4

公开(公告)日：2018-07-04

申请号：EP15870562

申请日：2015-11-16

Applicant: INTEL CORP

Inventor： WANG CHENG ,  WU YOUFENG ,  BAGHSORKHI SARA S ,  HARTONO ALBERT ,  VALENTINE ROBERT

IPC: G06F9/30 ,  G06F8/41 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/528 ,  G06F8/41 ,  G06F8/4451 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F12/0828 ,  G06F12/0875 ,  G06F2212/452

Abstract: Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.

公开(公告)号：EP2972796A4

公开(公告)日：2016-10-26

申请号：EP14763196

申请日：2014-01-14

Applicant: INTEL CORP

Inventor： GOTTSCHLICH JUSTIN E ,  PEREIRA CRISTIANO LIGIERI ,  POKAM GILLES ,  WU YOUFENG

IPC: G06F9/38 ,  G06F9/46 ,  G06F11/36

CPC classification number: G06F9/52 ,  G06F11/3632

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied.

Abstract translation: 公开了方法，装置，系统和制品以管理并发谓词表达。 一个示例性方法公开了将第一条件钩插入到第一线程中，与第一条件相关联的第一条件钩，将第二条件钩插入到第二线程中，与第二条件相关联的第二条件钩，防止第二线程执行 直到满足第一条件，并且当满足第二条件时识别并发冲突。

公开(公告)号：DE102018002525A1

公开(公告)日：2018-10-04

申请号：DE102018002525

申请日：2018-03-27

Applicant: INTEL CORP

Inventor： MEKKAT VINEETH ,  AGRON JASON M ,  WU YOUFENG

IPC: G06F9/38

Abstract: Eine Verarbeitungsvorrichtung, die umfasst: ein erstes Schattenregister, ein zweites Schattenregister und eine Befehlsausführungsschaltung, die kommunikationstechnisch mit dem ersten Schattenregister und dem zweiten Schattenregister gekoppelt ist und zu Folgendem ausgelegt ist: Empfangen einer Sequenz von Befehlen, die einen ersten lokalen Festschreibungsmerker, einen ersten globalen Festschreibungsmerker und einen ersten Registerzugriffsbefehl, der auf ein Architekturregister verweist, umfasst, spekulatives Ausführen des ersten Registerzugriffsbefehls, um einen spekulativen Registerzustandswert zu erzeugen, der einem physischen Register zugeordnet ist, als Antwort auf das Identifizieren der ersten lokalen Festschreibungsmerkers, Speichern des spekulativen Registerzustandswerts in dem ersten Schattenregister, und, als Antwort auf das Identifizieren des ersten globalen Festschreibungsmerkers, Speichern des spekulativen Registerzustandswerts in dem zweiten Schattenregister.

公开(公告)号：SG188993A1

公开(公告)日：2013-05-31

申请号：SG2013018742

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：DE10393481B4

公开(公告)日：2009-02-12

申请号：DE10393481

申请日：2003-09-12

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/45 ,  G06F9/00 ,  G06F12/08

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.

公开(公告)号：AU2002332811A1

公开(公告)日：2003-04-14

申请号：AU2002332811

申请日：2002-08-30

Applicant: INTEL CORP A DELAWERE CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/45 ,  G06F9/38

公开(公告)号：AU2002252163A1

公开(公告)日：2002-10-08

申请号：AU2002252163

申请日：2002-02-28

Applicant: INTEL CORP

Inventor： WU YOUFENG

IPC: G06F11/36

公开(公告)号：AU2011276656B2

公开(公告)日：2015-08-20

申请号：AU2011276656

申请日：2011-06-22

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG C ,  BRETERNITZ MAURICIO JR ,  LIU WEI

IPC: G06F1/32 ,  G06F9/38 ,  G06F9/46

Abstract: An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co- designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.

公开(公告)号：AU2011305091A1

公开(公告)日：2013-03-14

申请号：AU2011305091

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/06 ,  G06F9/30

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.