公开(公告)号：BR0207798A

公开(公告)日：2004-07-06

申请号：BR0207798

申请日：2002-02-22

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH ,  ZHANG HAITAO ,  ZOU QUIZHEN ,  JHA SANJAY

IPC: H01L25/18 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07

Abstract: Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface.

公开(公告)号：CA2704894A1

公开(公告)日：2001-06-21

申请号：CA2704894

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G11C16/02 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/06 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：ES2874481T3

公开(公告)日：2021-11-05

申请号：ES06784623

申请日：2006-06-06

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  ABDI BEHROOZ ,  SCOTT CLIFTON ,  FOK KENNY ,  CASSETT TIA ,  HWANG JIHYUN

IPC: H04W8/24 ,  G06F21/50 ,  H04W12/12

Abstract: Un sistema de comunicación que comprende un dispositivo de comunicación inalámbrica y un servidor (104), en el que el dispositivo de comunicación inalámbrica (102) incluye: una memoria (186) que comprende instrucciones ejecutables, un tipo de dispositivo correspondiente a dispositivo inalámbrico y una configuración de autorización (118) que tiene un esquema de autorización (194) que identifica al menos una de instrucciones ejecutables autorizadas e instrucciones ejecutables no autorizadas, en la que el esquema de autorización se basa en el tipo de dispositivo; y un módulo de autorización de instrucciones ejecutables (114) residente en la memoria, comprendiendo el módulo de autorización de instrucciones ejecutables lógica de autorización (116) operativa para explorar instrucciones ejecutables en la memoria y generar un registro basándose en la configuración de autorización, comprendiendo el registro instrucciones ejecutables no autorizadas basándose en el esquema de autorización, en el que el módulo de autorización de instrucciones ejecutables se puede operar para transmitir el registro generado al servidor para determinar si las instrucciones en el registro están autorizadas o no.

公开(公告)号：AT424609T

公开(公告)日：2009-03-15

申请号：AT02704175

申请日：2002-01-18

Applicant: QUALCOMM INC

Inventor： ANTONIO FRANKLIN ,  JHA SANJAY

IPC: G11B19/26 ,  G11B20/10

Abstract: A method and apparatus for a variable mode multi-media data object storage device. Large digital objects can be quickly downloaded in approximately a minute. The digital objects can be utilized or played back at real-time speeds. Utilization or playback consumes minimal power, allowing the disk to support portable devices operating on battery power. The storage device uses multiple disk rotation speeds to support multiple modes of operation. The storage device operates in at least two modes of disk drive operation, supporting a fast platter rotation speed for writing and a slower platter rotation speed for reading. The multiple rotation speeds operate in conjunction with a head assembly configured with at least one head for reading and multiple heads for writing. When writing, the disk spins at the faster rotation speed. When in utilization or playback mode, the disk spins at the slower, power conserving rotation speed.

公开(公告)号：AT339764T

公开(公告)日：2006-10-15

申请号：AT00986483

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：AU2002238123A1

公开(公告)日：2002-09-19

申请号：AU2002238123

申请日：2002-02-22

Applicant: QUALCOMM INC

Inventor： ZHANG HAITAO ,  JHA SANJAY ,  BAZARJANI SEYFOLLAH ,  ZOU QUIZHEN

IPC: H01L25/18 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  G01R31/3167

Abstract: Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface.

公开(公告)号：AU2002237873A1

公开(公告)日：2002-07-30

申请号：AU2002237873

申请日：2002-01-18

Applicant: QUALCOMM INC

Inventor： ANTONIO FRANKLIN P ,  JHA SANJAY

IPC: G11B20/10 ,  G11B19/26

Abstract: A method and apparatus for a variable mode multi-media data object storage device. Large digital objects can be quickly downloaded in approximately a minute. The digital objects can be utilized or played back at real-time speeds. Utilization or playback consumes minimal power, allowing the disk to support portable devices operating on battery power. The storage device uses multiple disk rotation speeds to support multiple modes of operation. The storage device operates in at least two modes of disk drive operation, supporting a fast platter rotation speed for writing and a slower platter rotation speed for reading. The multiple rotation speeds operate in conjunction with a head assembly configured with at least one head for reading and multiple heads for writing. When writing, the disk spins at the faster rotation speed. When in utilization or playback mode, the disk spins at the slower, power conserving rotation speed.

公开(公告)号：CA2704893A1

公开(公告)日：2001-06-21

申请号：CA2704893

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G11C16/02 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：WO02058064A2

公开(公告)日：2002-07-25

申请号：PCT/US0201553

申请日：2002-01-18

Applicant: QUALCOMM INC

Inventor： ANTONIO FRANKLIN P ,  JHA SANJAY

IPC: G11B20/10 ,  G11B19/26 ,  G11B15/00

CPC classification number: G11B5/02 ,  G11B19/26

Abstract: A method and apparatus for a variable mode multi-media data object storage device. Large digital objects can be quickly downloaded in approximately a minute. The digital objects can be utilized or played back at real-time speeds. Utilization or playback consumes minimal power, allowing the disk to support portable devices operating on battery power. The storage device uses multiple disk rotation speeds to support multiple modes of operation. The storage device operates in at least two modes of disk drive operation, supporting a fast platter rotation speed for writing and a slower platter rotation speed for reading. The multiple rotation speeds operate in conjunction with a head assembly (106) configured with at least one head (202) for reading and multiple heads (204) for writing. When writing, the disk spins at the faster rotation speed. When in utilization or playback mode, the disk spins at the slower, power conserving rotation speed.

Abstract translation: 一种用于可变模式多媒体数据对象存储装置的方法和装置。 大型数字物体可以在一分钟内快速下载。 可以以实时速度利用或播放数字对象。 利用率或播放功耗消耗最小，允许磁盘支持使用电池供电的便携式设备。 存储设备使用多个磁盘旋转速度来支持多种操作模式。 存储设备以至少两种磁盘驱动器模式运行，支持快速的盘片旋转速度以及较慢的盘片旋转速度进行读取。 多个旋转速度与配置有用于读取的至少一个头部（202）和用于书写的多个头部（204）的头部组件（106）一起操作。 写入时，磁盘以更快的旋转速度旋转。 在使用或播放模式下，磁盘以较慢的省电转速旋转。

公开(公告)号：WO0145106A2

公开(公告)日：2001-06-21

申请号：PCT/US0034216

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C

CPC classification number: G11C16/26 ,  G11C16/22 ,  G11C2216/22

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

Abstract translation: 闪存和SRAM存储器（112,113）嵌入专用集成电路（ASIC）中以提供改进的访问时间，并且还减少采用ASIC的移动电话的所有功耗。 闪存系统（112）包括被配置为提供一组单独的闪存宏的闪存阵列（130）和用于访问闪存宏的闪存控制器（132）。 闪速存储器控制器包括用于在从另一个闪存宏读取同时从闪存宏中的一个闪存宏写入的写入单元（144,146）。 闪存控制器还包括可编程等待状态寄存器（138）和密码寄存器（140），为闪存阵列的不同部分提供单独的密码。 提供存储器交换单元（149），用于在完成由引导加载程序执行的操作之后交换高和低存储器。 公开了方法和设备实现。