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    MULTIPLEX MODULES FOR CARRIER AGGREGATION RECEIVERS
    21.
    发明申请
    MULTIPLEX MODULES FOR CARRIER AGGREGATION RECEIVERS 审中-公开
    用于载波聚合接收机的多模块模块

    公开(公告)号：WO2015175094A1

    公开(公告)日：2015-11-19

    申请号：PCT/US2015/022055

    申请日：2015-03-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： TASIC, Aleksandar Miodrag ,  NARATHONG, Chiewcharn ,  HOLENSTEIN, Christian ,  PAN, Dongling ,  TANG, Yiwu ,  RANGARAJAN, Rajagopalan ,  LEUNG, Lai Kan

    IPC: H04B1/00 ,  H03F1/22

    CPC classification number: H04L27/2653 ,  H03F1/223 ,  H03F3/193 ,  H03F3/245 ,  H04B1/0064 ,  H04L45/16 ,  H04L45/245

    Abstract: Multiplex modules for use in carrier aggregation receivers are disclosed. In an exemplary embodiment, an apparatus includes an LNA multiplexer configured to receive a plurality of RF signals at a plurality of input terminals and to combine the RF signals into a combined RF signal that is output from an output terminal. The apparatus also includes an LNA demultiplexer configured to receive the combined RF signal at an input port that is connected to the output terminal and to distribute the combined RF signal to a plurality of output ports.

    Abstract translation: 公开了用于载波聚合接收机的多路复用模块。 在示例性实施例中，一种装置包括LNA多路复用器，其被配置为在多个输入端子处接收多个RF信号，并将RF信号组合成从输出端输出的组合RF信号。 该装置还包括LNA解复用器，其被配置为在连接到输出端子的输入端口处接收组合的RF信号，并将组合的RF信号分配到多个输出端口。

    PHASE-LOCKED LOOP USING DUAL LOOP MODE TO ACHIEVE FAST RESETTLING
    23.
    发明申请
    PHASE-LOCKED LOOP USING DUAL LOOP MODE TO ACHIEVE FAST RESETTLING 审中-公开
    使用双循环模式的相位锁定环来实现快速重置

    公开(公告)号：WO2014133783A1

    公开(公告)日：2014-09-04

    申请号：PCT/US2014/016383

    申请日：2014-02-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHEN, Xinhua ,  TANG, Yiwu

    IPC: H03L7/093 ,  H03L7/107

    CPC classification number: H03L7/0891 ,  H03L7/093 ,  H03L7/107

    Abstract: A PLL operates in a first low bandwidth mode using a first control loop and in a second high bandwidth mode using a second control loop. The PLL includes a VCO that generates an output signal at a desired frequency used by a transmitter. When the transmitter switches from a High Power mode (HP TX) to a Low Power mode (LP TX), the PLL is perturbed (VCO no longer generates the desired frequency) and must resettle within an allocated time. In one example, the VCO frequency is 3.96 GHz and the settling time requirement is 25 microseconds. Upon switching from HP TX to LP TX, the PLL is switched to the second high bandwidth mode 15 microseconds and is then switched back to the first low bandwidth mode. The PLL resettles to within 1ppm of the initial VCO frequency of 3.96 GHz within the allocated 25 microseconds.

    Abstract translation: PLL使用第一控制环路在第一低带宽模式下工作，并且在第二高带宽模式中使用第二控制环路工作。 PLL包括VCO，其产生以发射机使用的期望频率的输出信号。 当发射机从高功率模式（HP TX）切换到低功耗模式（LP TX）时，PLL被扰乱（VCO不再产生所需频率），并且必须在分配的时间内重新定位。 在一个示例中，VCO频率为3.96GHz，建立时间要求为25微秒。 从HP TX切换到LP TX时，PLL将切换到第二个高带宽模式15微秒，然后切换回第一个低带宽模式。 在分配的25微秒内，PLL将重置为3.96 GHz的初始VCO频率的1ppm以内。

    PHASE-LOCKED LOOP (PLL) WITH MULTIPLE ERROR DETERMINERS
    25.
    发明申请
    PHASE-LOCKED LOOP (PLL) WITH MULTIPLE ERROR DETERMINERS 审中-公开

    公开(公告)号：WO2022046339A1

    公开(公告)日：2022-03-03

    申请号：PCT/US2021/043311

    申请日：2021-07-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHAO, Yue ,  ZANUSO, Marco ,  RANGARAJAN, Rajagopalan ,  TANG, Yiwu

    IPC: H03L7/087 ,  H03L7/081 ,  H03L7/197 ,  H03L7/089 ,  H03L7/183

    Abstract: An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.

    AVOIDING SPURIOUS RESPONSES WITH RECONFIGURABLE LO DIVIDERS
    27.
    发明申请
    AVOIDING SPURIOUS RESPONSES WITH RECONFIGURABLE LO DIVIDERS 审中-公开
    避免与可重新启动的分路器的特殊反应

    公开(公告)号：WO2015175138A1

    公开(公告)日：2015-11-19

    申请号：PCT/US2015/025991

    申请日：2015-04-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： RANGARAJAN, Rajagopalan ,  NARATHONG, Chiewcharn ,  LEUNG, Lai Kan ,  PAN, Dongling ,  TASIC, Aleksandar Miodrag ,  TANG, Yiwu

    IPC: H04B1/00 ,  H04B15/06

    CPC classification number: H04W72/0453 ,  H04B1/005 ,  H04B15/06 ,  H04L45/245 ,  H04W88/06

    Abstract: Methods and apparatus including: setting up a plurality of configurations for a plurality of local oscillator (LO) paths of a carrier aggregation (CA) transceiver operating with a plurality of bands; calculating and comparing frequencies for each LO path of the plurality of LO paths and at least one divider ratio of LO dividers for each band of the plurality of bands to identify frequency conflicts; and reconfiguring the LO dividers for the plurality of LO paths and the plurality of bands when the frequency conflicts are identified.

    Abstract translation: 一种方法和装置，包括：为多个频带操作的载波聚合（CA）收发机的多个本地振荡器（LO）路径建立多个配置; 计算和比较所述多个LO路径中的每个LO路径的频率和所述多个频带中的每个频带的LO分频器的至少一个分频比，以识别频率冲突; 以及当识别出频率冲突时，为多个LO路径和多个频带重新配置LO分频器。

    Ku ADAPTATION FOR PHASE-LOCKED LOOP WITH TWO-POINT MODULATION
    28.
    发明申请
    Ku ADAPTATION FOR PHASE-LOCKED LOOP WITH TWO-POINT MODULATION 审中-公开
    Ku适用于具有两点调制的锁相环

    公开(公告)号：WO2014059291A1

    公开(公告)日：2014-04-17

    申请号：PCT/US2013/064569

    申请日：2013-10-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： LEUNG, Lai Kan ,  TANG, Yiwu ,  NARATHONG, Chiewcharn

    IPC: H04B1/30

    CPC classification number: H04B1/62 ,  H04B1/30

    Abstract: A wireless device includes: an antenna; and a polar-modulation transmitter coupled to the antenna and configured for two-point modulation, the transmitter including: a data input; a first signal path including a multiplier coupled to the data input and a voltage-controlled oscillator gain adaptation module coupled to the multiplier and configured to provide a gain value to the multiplier; and a second signal path coupled to the data input and including an analog phase-locked loop (PLL) including a voltage-controlled oscillator (VCO) coupled to the first signal path.

    Abstract translation: 无线设备包括：天线; 以及耦合到所述天线并被配置为用于两点调制的极性调制发射机，所述发射机包括：数据输入; 包括耦合到数据输入的乘法器的第一信号路径和耦合到乘法器并被配置为向乘法器提供增益值的压控振荡器增益适配模块; 以及耦合到所述数据输入并且包括模拟锁相环（PLL）的第二信号路径，所述模拟锁相环包括耦合到所述第一信号路径的压控振荡器（VCO）。

    SYSTEM AND METHOD OF DETERMINING AN OSCILLATOR GAIN
    29.
    发明申请
    SYSTEM AND METHOD OF DETERMINING AN OSCILLATOR GAIN 审中-公开
    确定振荡器增益的系统和方法

    公开(公告)号：WO2014018893A1

    公开(公告)日：2014-01-30

    申请号：PCT/US2013/052331

    申请日：2013-07-26

    Applicant: QUALCOMM INCORPORATED

    Inventor： TANG, Yiwu ,  ZHU, Yunliang ,  NARATHONG, Chiewcharn ,  RONG, Sujiang

    IPC: H03L7/07

    CPC classification number: H03L7/099 ,  G01R31/2832 ,  H03B21/01 ,  H03L7/07

    Abstract: A method includes generating a first signal based on a difference between a first frequency of a first voltage controlled oscillator (VCO) and a second frequency of a second VCO. The method further includes determining a gain of the first VCO at least partially based on the first signal.

    Abstract translation: 一种方法包括基于第一压控振荡器（VCO）的第一频率和第二VCO的第二频率之间的差产生第一信号。 该方法还包括至少部分地基于第一信号来确定第一VCO的增益。

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