公开(公告)号：DE602004015029D1

公开(公告)日：2008-08-28

申请号：DE602004015029

申请日：2004-08-27

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK ,  TOMEI AMBROISE

IPC: G06F7/58 ,  H03K3/84 ,  G09C1/00

Abstract: The state of an output bit is conditioned to respective states of the bits of the initial flow examined by multibit words of identical lengths. The state of the current output bit is conditioned to the state of previous output bit, upon occurrence of word of bits of identical states. An independent claim is also included for bitflow normalization circuit.

公开(公告)号：DE602004001293D1

公开(公告)日：2006-08-03

申请号：DE602004001293

申请日：2004-06-25

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN

IPC: G06F1/00 ,  G06F21/52 ,  G06F21/55

Abstract: The number of occurrences of operation during program execution are incremented and memorized, by comparing each operation with pre-established list. Number of occurrences are compared with previously stored ranges assigned to each operation at the end of execution. The ranges are determined by analyzing possible statistics deviations of the number of occurrences with respect to program execution. An independent claim is also included for processor for executing program.

公开(公告)号：DE60023770T2

公开(公告)日：2006-06-01

申请号：DE60023770

申请日：2000-02-18

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  ROMAIN FABRICE ,  PLESSIER BERNARD ,  HENNEBOIS BRIGITTE

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30

Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.

公开(公告)号：DE60114007D1

公开(公告)日：2006-02-23

申请号：DE60114007

申请日：2001-06-18

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  MUSSARD BRUNO

IPC: G06F12/14 ,  G06F1/00 ,  G06F21/06 ,  G06F21/24 ,  G06K19/073 ,  G11C16/02 ,  G11C16/22

Abstract: A circuit to detect the use of an element of an integrated circuit may include a non-volatile electrically programmable storage circuit and a programming circuit. The programming circuit may be used to partially program the storage circuit and gradually modify its programming level as the element is used so that the level represents the number of uses of the element.

公开(公告)号：DE60004449D1

公开(公告)日：2003-09-18

申请号：DE60004449

申请日：2000-06-22

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN

IPC: G06F7/72

公开(公告)号：DE602004023436D1

公开(公告)日：2009-11-12

申请号：DE602004023436

申请日：2004-03-29

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

Inventor： TEGLIA YANNICK ,  ROMAIN FABRICE ,  LIARDET PIERRE-YVAN ,  FRAGNETO PASQUALINA ,  SOZZANI FABIO ,  BERTONI GUIDO

IPC: H04L9/06

Abstract: A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.

公开(公告)号：DE602005015157D1

公开(公告)日：2009-08-13

申请号：DE602005015157

申请日：2005-05-10

Applicant: ST MICROELECTRONICS SA

Inventor： ELIAS PIERRE ,  LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: G06F9/32 ,  G06F21/55

公开(公告)号：DE602006004797D1

公开(公告)日：2009-03-05

申请号：DE602006004797

申请日：2006-07-05

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN

IPC: H04L9/32

Abstract: The method involves partitioning a digital quantity into blocks of identical size, and applying a symmetrical encryption algorithm to each block. A one-to-one, non linear function (FCT) is applied to a result (MAC) of the previous steps for obtaining a current value (AUTH) that is to be compared with an expected value provided from the exterior of a processor. Each block is combined with the result provided by the algorithm from the previous block. Independent claims are also included for the following: (1) an integrated processor comprising a unit for implementing a method for verifying a digital quantity (2) a mobile telephone comprising a processor.

公开(公告)号：AT407494T

公开(公告)日：2008-09-15

申请号：AT05106111

申请日：2005-07-05

Applicant: PROTON WORLD INT NV ,  ST MICROELECTRONICS SA

Inventor： DAEMEN JOAN ,  GUILLEMIN PIERRE ,  ANGUILLE CLAUDE ,  BAEDOUILLET MICHEL ,  LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: H04L9/18 ,  G06F12/14 ,  G06F21/00

Abstract: The method involves applying a ciphering algorithm with a function of a key specific to an integrated circuit of an initialization vector. A ciphered data is memorized, where the initialization vector includes a storage address of the data in a memory and a differentiation value. An algorithm identical to the ciphering algorithm is applied based on the address of the ciphered data. An independent claim is also included for a smart card comprising an electronic assembly.

公开(公告)号：DE602004001293T2

公开(公告)日：2007-05-31

申请号：DE602004001293

申请日：2004-06-25

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN

IPC: G06F1/00 ,  G06F21/52 ,  G06F21/55

Abstract: The number of occurrences of operation during program execution are incremented and memorized, by comparing each operation with pre-established list. Number of occurrences are compared with previously stored ranges assigned to each operation at the end of execution. The ranges are determined by analyzing possible statistics deviations of the number of occurrences with respect to program execution. An independent claim is also included for processor for executing program.