公开(公告)号：FR2817417B1

公开(公告)日：2003-01-24

申请号：FR0015307

申请日：2000-11-28

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  NARCHE PASCAL ,  RUAT LUDOVIC

IPC: G01R31/317 ,  G06F11/22 ,  H03K21/38 ,  G06F11/30 ,  G06F13/00 ,  H03K19/003

公开(公告)号：FR2788353B1

公开(公告)日：2001-02-23

申请号：FR9900301

申请日：1999-01-11

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK

IPC: G06F12/14 ,  G06F9/445

Abstract: The secure access system accesses a microprocessor with an address and digital word bus and a register (3) and address decoder (2). A number of protection circuits (1) are associated with the register providing access. After initialization (RESET) of the microprocessor access is blocked, only allowing access after sending a set of N digital pass words during the first operation set.

公开(公告)号：FR2821456B1

公开(公告)日：2003-06-20

申请号：FR0102701

申请日：2001-02-28

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  CAVALLI DIDIER

IPC: G06F12/06 ,  G06F13/16 ,  G06F13/36 ,  G06F13/40 ,  G06F15/76 ,  G06F13/368

Abstract: A microprocessor is connected to a first memory space through a first bus and to a second memory space through a second bus. The microprocessor includes a processing unit that includes a program bus and a data bus, and an interface unit connected, on one side, to the program bus and to the data bus and, on the other side, to the first and second buses. The interface includes a switching circuit for connecting the program bus and the data bus, respectively, to either the first bus or the second bus, in accordance with respective requests for accessing the program and data sent by the processing unit.

公开(公告)号：FR2831289A1

公开(公告)日：2003-04-25

申请号：FR0113478

申请日：2001-10-19

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  BASSET PHILIPPE

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/34 ,  G06F9/355 ,  G06F12/02 ,  G06F9/44 ,  G06F15/00

Abstract: The microprocessor comprises a processing unit (1) and an addressable memory space (2). This comprises a base memory zone (2a) and an extended memory zone (2b). Two instruction sets are provided for accessing the two respective memory zones, such that when one set is in use, access may only be gained to the respective memory zone. The microprocessor comprises a processing unit (1) and a connection system with access to an addressable memory space (2). The processor is able to execute the instructions derived from a set comprising instructions for accessing the memory space. The memory space has a base memory zone (2a) and an extended memory zone (2b). The instruction set includes a first set of instructions for accessing the base memory zone and a second set of instructions for accessing the extended memory zone. The microprocessor includes a system for preventing any access to the extended memory zone when the processor is executing instructions from the first instruction set. The microprocessor is thus forced to use the appropriate memory region when executing instructions from one or other of the two memory areas.

公开(公告)号：FR2817432A1

公开(公告)日：2002-05-31

申请号：FR0015387

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  TARAYRE PIERRE

IPC: H04L7/04 ,  G06F13/42 ,  H04L29/08 ,  G06F15/163

Abstract: Two devices (D1,D2) may transmit data using clock thread (CK) and at least a data thread (DT). The clock thread is maintained by default to a logical value A that may be converted to an electric potential representing a logical value B inverse of A. The two devices may convert B to the CK at the time of data transmission. A target device to which the data is sent does not loose the CK since it does not read the data. The data-sending device maintains it until the CK is released by the device to which data is targeted. Independent claims are included for: (a) a data transmission-reception device (b) a synchronous data transmission device (c) an interface circuit for data transmission in master-slave configuration

公开(公告)号：DE60000112D1

公开(公告)日：2002-05-16

申请号：DE60000112

申请日：2000-01-06

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK

IPC: G06F12/14

Abstract: The secure access system accesses a microprocessor with an address and digital word bus and a register (3) and address decoder (2). A number of protection circuits (1) are associated with the register providing access. After initialization (RESET) of the microprocessor access is blocked, only allowing access after sending a set of N digital pass words during the first operation set.

公开(公告)号：FR2789501A1

公开(公告)日：2000-08-11

申请号：FR9901517

申请日：1999-02-09

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK

IPC: G06F1/32

Abstract: During active stop mode micro-controller its CPU, peripheral circuits (MEM,ADC,DAC) and a clock (CLKTR) are suspended, including main oscillator functions and delivering an oscillating signal (fosc). An internal circuit (DIV) is activated by the oscillating signal (fosc) generation due to an internal interruption. This action brings back the micro-controller (MCU) in its operation mode. An Independent claim is included for: (a) a device for limiting a power consumption of a micro-controller

公开(公告)号：FR2788353A1

公开(公告)日：2000-07-13

申请号：FR9900301

申请日：1999-01-11

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK

IPC: G06F12/14 ,  G06F9/445

Abstract: The secure access system accesses a microprocessor with an address and digital word bus and a register (3) and address decoder (2). A number of protection circuits (1) are associated with the register providing access. After initialization (RESET) of the microprocessor access is blocked, only allowing access after sending a set of N digital pass words during the first operation set.