公开(公告)号：FR2828766B1

公开(公告)日：2004-01-16

申请号：FR0110866

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L23/498 ,  H01L21/60

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

公开(公告)号：FR2830365A1

公开(公告)日：2003-04-04

申请号：FR0112519

申请日：2001-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  MAZOYER PASCALE ,  FAZAN PIERRE

IPC: G11C7/06 ,  G11C7/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40

Abstract: A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.

公开(公告)号：FR2828764A1

公开(公告)日：2003-02-21

申请号：FR0110868

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: The invention relates to an integrated circuit comprising: a capacitor (23) which is disposed on top of a substrate (1) inside a first cavity in a dielectric material; a first electrode; a second electrode; a fine dielectric layer which is disposed between the two electrodes; and a structure (7) which connects to the capacitor. Said connecting structure is disposed at the same level as the capacitor in a second cavity which is narrower than the first, said second cavity being entirely filled up by an extension of at least one of the electrodes of the capacitor.

公开(公告)号：FR2784798B1

公开(公告)日：2002-03-01

申请号：FR9813034

申请日：1998-10-14

Applicant: ST MICROELECTRONICS SA

Inventor： CIAVATTI JEROME ,  MAZOYER PASCALE

IPC: H01L21/8242