公开(公告)号：IT1250908B

公开(公告)日：1995-04-21

申请号：IT2072890

申请日：1990-06-22

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  VAI GIANFRANCO ,  ZUFFADA MAURIZIO ,  BETTI GIORGIO

IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948 ,  H01L

Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).

公开(公告)号：DE60130885D1

公开(公告)日：2007-11-22

申请号：DE60130885

申请日：2001-08-10

Applicant: IBM ,  ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  BETTI GIORGIO ,  CHRAPPAN SOLDAVINI F STMICROEL ,  HASSNER MARTIN AURELIANO

IPC: H01L21/822 ,  H03H11/48 ,  H01L27/04

Abstract: The invention relates to a non-linear electronic device and, more particularly, to a non-linear inductor. More specifically, but not exclusively, the invention relates to an electronic circuit device that may be integrated on a semiconductor substrate. Advantageously, the non-linear device is a inductor formed by a feedback loop of cascade connected active blocks (2, 5, 6). Moreover, the invention may be integrated or used in association with a circuit network including other non-linear devices.

公开(公告)号：ITMI20011309A1

公开(公告)日：2002-12-23

申请号：ITMI20011309

申请日：2001-06-21

Applicant: ST MICROELECTRONICS SRL

Inventor： BETTI GIORGIO ,  PAU DANILO ,  DATI ANGELO ,  D ALTO VIVIANA ,  SANTINELLO FILIPPO

IPC: H04N7/26 ,  H04N7/50 ,  H04N7/66

Abstract: A method of storing a data file, particularly in the MPEG format and including a flow of different frames, comprises a protection system for the data file based on a parameter stored in the data file. Advantageously, the storage method comprises selectively protecting the frames by storing parameters that are associated with corresponding different frames whose values are selected to provide a playing quality level requested by an end user. Also, a method is provided for decoding a data file, particularly of the MPEG type and including a flow of different frames, wherein the data file is stored per above.

公开(公告)号：DE69128987D1

公开(公告)日：1998-04-09

申请号：DE69128987

申请日：1991-06-17

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  VAI GIANFRANCO ,  ZUFFADA MAURIZIO ,  BETTI GIORGIO

IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948

Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).

公开(公告)号：DE69031863D1

公开(公告)日：1998-02-05

申请号：DE69031863

申请日：1990-10-17

Applicant: ST MICROELECTRONICS SRL

Inventor： SACCHI FABRIZIO ,  LIETAR LOIC ,  VAI GIANFRANCO ,  BETTI GIORGIO

IPC: H03K3/0233 ,  H03K3/2897 ,  H03K3/023

Abstract: An electronic comparator device (1) with hysteresis, being of a type which comprises a differential cell (2) having a signal input (IN), an output (OUT), and a threshold input (S), further comprises a second differential cell (9) having one input (B9) connected to said output (OUT) and the other input (B10) connected to a controlling circuit portion (10) which has an output (E11) connected to the threshold input (S) to reduce the threshold voltage value (Vs) stepwise on the first change-over of the output (OUT) of the comparator (1).

公开(公告)号：DE69327053T2

公开(公告)日：2000-02-24

申请号：DE69327053

申请日：1993-09-21

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  BETTI GIORGIO ,  ALINI ROBERTO

IPC: G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14

Abstract: In a decoder for decoding a serial data stream, employing an extracted base clock signal, synchronous with an input, coded, serial data stream, a fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary clock signal for synthesizing a pre-decoded value produced by a first combinative logic network within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop, a pipelined operation is implemented by momentarily storing the bits that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock the processing by said first combinative network of the n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the raising front of the outpunt sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating spead may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.

公开(公告)号：IT9020728D0

公开(公告)日：1990-06-22

申请号：IT2072890

申请日：1990-06-22

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  VAI GIANFRANCO ,  ZUFFADA MAURIZIO ,  BETTI GIORGIO

IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948

Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).