中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

70 records (took 0.025 seconds)

    25.
    发明专利
    未知

    公开(公告)号：DE69919500T2

    公开(公告)日：2005-09-08

    申请号：DE69919500

    申请日：1999-02-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  GROSSO ANTONIO

    IPC: H03F3/217 ,  H03M1/68 ,  H03M1/82

    Abstract: A digital input PWM power amplifier comprises: an oversampling and noise shaping circuit receiving pulse code modulated (PCM) digital input data organized in words of a first number M of bits at a certain bit rate (Fin) and outputting pulse code modulated digital data organized in words of a smaller number N of bits at a multiple bit rate (Fin*K); a first bus transmitting a first number (P) of most significant bits (MSB) of said N bit words output from said first circuit and a second bus transmitting a second number (S) of least significant bits of said N bit words output from said first circuit; first and second PCM/PWM converters, respectively fed with said first and second number of bits transmitted through said first and said second bus, each converter including a counter driven by a clock signal (Fclock) of frequency equal to the product of the bit rate (Fin*K) of the MSB and LSB bits transmitted on the respective bus and the square of the respective number of bits (P, S) generating reference digital words composed of said respective number of bits (P, S), defining ramps of digital values with a frequency identical to said multiple bit rate (Fin*K), and a digital comparator receiving through a first input said reference digital words and through a second input the respective first and second number of bits (MSB, LSB) and outputting a respective PWM signal (MSBdig, LSBdig); the PWM signal (MSBig) output by said first converter, being summed to the so attenuated PWM signal (LSBdig) output by said second converter on the inverting input node (-) of said output power stage.

    26.
    发明专利
    未知

    公开(公告)号：IT1320694B1

    公开(公告)日：2003-12-10

    申请号：ITTO20000931

    申请日：2000-10-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MERONI CRISTIANO ,  BOTTI EDOARDO ,  BASCHIROTTI ANDREA ,  GHIONI MASSIMO

    IPC: H03M1/06 ,  H03M1/74

    Abstract: A method for digital-to-analog conversion of a digital input code into a first output analog signal and a second output analog signal to be supplied to a first terminal and a second terminal, respectively, of an audio load, the conversion being performed by means of a DAC with N-level balanced output, the conversion method includes using N/2 positive generator elements supplying respective positive elementary contributions which are nominally equal to one another, and N/2 negative generator elements supplying respective negative elementary contributions which are nominally equal to one another and, in absolute value, equal to the positive elementary contributions; attributing the same progressive addresses to the positive generator elements and to the negative generator elements; defining a first index for the positive input codes and a second index for the negative input codes; and, in the presence of an input code at the input of the DAC, selecting between the first index and the second index, the index corresponding to the sign of the input code; activating a first set of positive generator elements and a second set of negative generator elements, the number of the positive generator elements activated and the number of the negative generator elements activated being equal to one another and proportional to the input code, and the addresses of the positive generator elements activated and of the negative generator elements activated being a function of the selected index; generating the first output analog signal by summing the positive elementary contributions supplied by the positive generator elements activated, and generating the second output analog signal by summing the negative elementary contributions supplied by the negative generator elements activated; and updating the selected index according to the input code.

    27.
    发明专利
    未知

    公开(公告)号：DE69528958D1

    公开(公告)日：2003-01-09

    申请号：DE69528958

    申请日：1995-01-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  FERRARI PAOLO

    IPC: H01L21/8222 ,  H01L27/06 ,  H01L29/861 ,  H01L27/00 ,  H01L27/02

    Abstract: A monolithic output stage which is self-protected against the occurrence of incidental latch-up phenomena and integrated in a portion of a semiconductor material chip which is isolated by a peripheral barrier structure linked electrically to a terminal (Vcc), specifically a supply terminal being applied thereto a constant voltage (+Vcc), has the barrier structure coupled to the terminal (Vcc) through a forward biased diode (D1) from the terminal (Vcc). The integrated barrier structure is formed within a region (21'') having a first type of conductivity, and comprises a heavily doped well (29) having the first type of conductivity and a substantially annular shape and contacting a large surface of the chip (22). This structure is characterized in that, in at least one portion thereof close to contact regions (S) for connection to said terminal (Vcc), the barrier well (29) is split into first and second heavily doped concentrical regions (29' and 29'') having the first type of conductivity. The barrier structure further comprises, located at said portion, an intermediate region (30) which is less heavily doped and also has the first type of conductivity, and a surface region (31) with a second type of conductivity located within said intermediate region. The invention preferably involves a power output stage including a vertical PNP transistor isolated by said barrier well.

    28.
    发明专利
    未知

    公开(公告)号：DE69426935T2

    公开(公告)日：2001-08-02

    申请号：DE69426935

    申请日：1994-12-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  MANDRINI TIZIANA

    IPC: B60R16/02 ,  B60R16/03 ,  G05F1/10 ,  H02H3/20 ,  H02H7/06 ,  H02H7/20

    Abstract: A semiconductor electronic circuit with a protection device against supply voltage overloading, being of the type which comprises a first power circuit portion (2) connected to a power supply line (AL) and enabled through at least a first transistor (Q1). This transistor (Q1) has a control terminal driven by a voltage sensor (R1, R2, Z1) connected to the power supply line (AL). The semiconductor electronic circuit (1) is characterized, moreover, in that it comprises a second signal circuit portion (3) connected to the power supply line (AL) in a structurally independent manner of the first power circuit portion (2) and through a controlled switch (M1).

Patent Agency Ranking