公开(公告)号：JP2617095B2

公开(公告)日：1997-06-04

申请号：JP29488294

申请日：1994-11-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  COSTA RAFFAELE ,  TORRICELLI PIERO

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/22 ,  G11C16/06

公开(公告)号：JPH07287985A

公开(公告)日：1995-10-31

申请号：JP29488294

申请日：1994-11-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  COSTA RAFFAELE ,  TORRICELLI PIERO

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/22 ,  G11C16/06

Abstract: PURPOSE: To install the row of OTP elements into the memory-element matrix of an electrically erasable storage device without the trouble of reliability and operation by mounting a field-effect transistor as an electronic switch between an OTP-element control line and a ground. CONSTITUTION: In the matrix of a user memory element, at least one row OTP1 or OTP2 of one-time programmable(OTP) element sharing a line selective line D1 -D5 with other elements is added. These OTP elements have selective terminals connected to the row selective lines OTP1 , OTP2 in the same manner as other memory elements. The source terminals of the OTP elements in the rows of the OTP1 , OTP2 are connected to a device ground (GND) through common switching transistors M1 , M2 driven from the same row selective line. Accordingly, since the selective transistors M1 , M2 are controlled from the OTP row decoding lines OTP1 , OTP2 , an additional external control signal is unnecessitated for driving the switching transistors M1 , M2 of the OTP elements.

公开(公告)号：JPH0750397A

公开(公告)日：1995-02-21

申请号：JP4720894

申请日：1994-03-17

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To eliminate errors by reducing the number of memory cells which are excessively erased. CONSTITUTION: A memory array 20 is provided with control transistors 23 of a number of sections regarding sections 22 of memory cells 21. The control transistor of each section is an NMOS transistor, which has a drain terminal connected to a control bit line (BLP) of the transistor. Each control transistor for each section is related to a row part of the memory array. A control gate connected to each word line(WL) and a source region, connected to a source region in the memory cell in the same row and the same section, are presented.

公开(公告)号：DE69739864D1

公开(公告)日：2010-06-10

申请号：DE69739864

申请日：1997-11-05

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  FERRARIO DONATO ,  GOLLA CARLA MARIA

IPC: G11C16/00 ,  G11C5/14 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08

Abstract: A boosting circuit supplied by a first voltage level (Vcc) and a second voltage level (Gnd), and having an output line (13) capable of taking a third voltage level, characterized by comprising at least two distinct circuits (A1,11,A2,12) for generating said third voltage level, the at least two circuits selectively activatable for generating said third voltage level and selectively couplable to said output line (13).

公开(公告)号：DE60129788D1

公开(公告)日：2007-09-20

申请号：DE60129788

申请日：2001-02-14

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

IPC: G11C11/56 ,  G11C7/06 ,  G11C16/26

公开(公告)号：ITMI20050607A1

公开(公告)日：2006-10-12

申请号：ITMI20050607

申请日：2005-04-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  DOSSI ROBERTO ,  LOSAVIO ALDO ,  STOPPINO PIER PAOLO ,  VANALLI GIAN PIETRO

公开(公告)号：DE60205389D1

公开(公告)日：2005-09-08

申请号：DE60205389

申请日：2002-11-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  CAMPARDO GIOVANNI ,  GHILARDI TECLA

IPC: G11C16/34

公开(公告)号：DE69922637D1

公开(公告)日：2005-01-20

申请号：DE69922637

申请日：1999-06-04

Applicant: ST MICROELECTRONICS SRL ,  MITSUBISHI ELECTRIC CORP

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  OHBA ATSUSHI ,  CARRERA MARCELLO

IPC: G11C16/06 ,  G11C5/14 ,  G11C8/10 ,  G11C11/56 ,  G11C16/02 ,  G11C16/08 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948 ,  G11C16/12

Abstract: The switch circuit (40) receives a first supply voltage (VCC) and a second supply voltage (VPP) different from each other; a control input (41a) receiving a control signal that may be switched between the first supply voltage and ground; a driving inverter stage (44) supplied by the second supply voltage (VPP) and defining the output (70) of the circuit; a feedback inverter stage (43) supplied by the second supply voltage and including a top transistor (51) and a bottom transistor (53) defining an intermediate node (58) and having respective control terminals. The control terminal of the top transistor (51) is connected to the output node (70), the control terminal of the bottom transistor (53) is connected to the control input (41a), and the intermediate node is connected to the input (58) of the driving inverter stage. An activation element (80, 71) helps switching of the intermediate node (58) from the second supply voltage to ground; current limiting transistors (52, 62) are arranged in the inverter stages to limit the current flowing during switching and to reduce the consumption of the circuit.

公开(公告)号：DE69629668T2

公开(公告)日：2004-07-08

申请号：DE69629668

申请日：1996-06-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MACCARRONE MARCO

IPC: G11C16/06 ,  G11C16/28

公开(公告)号：DE69823659D1

公开(公告)日：2004-06-09

申请号：DE69823659

申请日：1998-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

IPC: G11C16/06 ,  G11C8/14 ,  G11C16/04 ,  G11C8/00