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    22.
    发明专利
    未知

    公开(公告)号：DE602006002886D1

    公开(公告)日：2008-11-06

    申请号：DE602006002886

    申请日：2006-07-28

    Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS ASIA ,  ST MICROELECTRONICS SRL

    Inventor： SEO DONGHYUN ,  MULATTI JACOPO ,  KANG TAEGYOUNG

    IPC: H03K17/22 ,  G01F1/24 ,  G01F1/28

    Abstract: A power on reset circuit for initializing at power on a digital integrated circuit comprising a first power on reset signal generator (PORE_GEN) supplied by an externally applied power supply voltage (VDDE), generating a first or external power on reset signal (PORE) during external power supply voltage (VDDE) ramp up, a reference voltage generator (REF_GEN) powered by said externally applied power supply voltage (VDDE) when enabled by said first power on reset signal (PORE) for generating a stable compensating reference voltage (VREF_VDC), a voltage down converter circuit (VDC) converting the externally applied power supply voltage (VDDE) to a stable regulated internal supply voltage (VDDI) employing said reference voltage (VREF_VDC) generated by the reference voltage generator, and a second or internal power on reset signal generator circuit (PORI_GEN) supplied at said stable regulated internal supply voltage (VDDI) and generating a second power on reset signal (PORI) conveyed to core parts of the integrated circuit for initializing them at power on, has the second internal power on reset signal generator circuit with enablement means for enabling also the second internal power on reset signal generator circuit with the first power on reset signal (PORE) together with the voltage down converter circuit (VDC). Fuse means permit optimization of dynamical responses of the two reset generators for selectably supported external power supply voltages.

    23.
    发明专利
    未知

    公开(公告)号：DE60207190D1

    公开(公告)日：2005-12-15

    申请号：DE60207190

    申请日：2002-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NUZZARELLO GIOVANNI ,  MULATTI JACOPO

    IPC: G11C5/14 ,  H02M3/07 ,  G05F3/20

    Abstract: It is describes a basic stage for a charge pump circuit having at least an input terminal (UP) and an output terminal (DOWN) and comprising: at least a first inverter inserted between said input and output terminals (UP, DOWN) and comprising a first complementary pair of transistors (MP1, MN1), defining a first internal node (XL), at least a second inverter inserted between said input and output terminals (UP, DOWN) and comprising a second complementary pair of transistors (MP2, MN2), defining a second internal node (XR), respective first and second capacitors (CL, CR) connected to said first and second internal nodes (XL, XR) and receiving a first and second driving signals (CK, CK_N); the first (MP1, MN1) and second (MP2, MN2) pairs of transistors having the control terminals cross-connected to the second (XR) and first (XL) internal node. Advantageously according to the invention, the basic stage comprises at least a first biasing structure (12) connected to the first and second internal nodes (XL, XR) and comprising a first (MN3) and second (MN4) biasing transistors, which are respectively coupled to said first and second inverters.

    26.
    发明专利
    未知

    公开(公告)号：ITMI991475A1

    公开(公告)日：2001-01-02

    申请号：ITMI991475

    申请日：1999-07-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MULATTI JACOPO ,  MACCARONE MARCO

    IPC: G11C5/14 ,  G11C16/12 ,  G11C16/30

    Abstract: Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference. A method is also presented for generating voltage references with a reduced value of settling time as produced within a memory architecture.

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