公开(公告)号：DE69328253T2

公开(公告)日：2000-09-14

申请号：DE69328253

申请日：1993-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA ,  PADOAN SILVIA

IPC: G11C5/14 ,  G11C16/06 ,  G11C17/00 ,  G11C16/30

Abstract: A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage (4) being powered between a first (VPP) and a second (GND) voltage reference and having a first input terminal connected to a resistive divider (2) of the first reference voltage (VPP) and an output terminal fed back to said input through a current mirror (3), and a source-follower transistor (MOUT) controlled by the output and connected to the cells through a programming line (VP). Also provided is a MOS transistor (MG2) which connects to ground the programming line (VP) and a corresponding resistive path (7) connected between the current mirror (3) and the second voltage reference (GND).

公开(公告)号：DE69422794T2

公开(公告)日：2000-06-08

申请号：DE69422794

申请日：1994-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PADOAN SILVIA ,  PASCUCCI LUIGI

IPC: G11C17/00 ,  G11C16/06 ,  H01L27/10 ,  H03K19/177

Abstract: The PLA (1), which implements a state machine of a nonvolatile memory, presents a dynamic NAND-NOT-NOR configuration, and the timing signals for correct reading of the PLA are generated by a clock generator (30) which generates a monostable succession of read enabling signals (CPPA, CPPO, CPM) on receiving a predetermined switching edge of an external clock signal (CP). The clock generator enables evaluation of the AND (3) and OR (4) planes of the PLA and subsequently storage of the results through sections (33, 38; 48) duplicating the propagation delays of the signals in the corresponding parts (3-5) of the PLA. Reading is terminated as soon as completion of the storage step is indicated, so that reading of the PLA lasts only as long as strictly necessary, thus preventing erroneous switching while at the same time ensuring correct reading of the PLA.

公开(公告)号：DE69424764T2

公开(公告)日：2000-11-16

申请号：DE69424764

申请日：1994-01-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  PADOAN SILVIA

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H02M3/07 ,  G11C5/00

Abstract: A charge pump circuit (1) including a number of pull-up stages (2) connected in parallel with one another between a reference potential line (3) and an output line (4). Each stage (2) includes a capacitor (5) having a first terminal connected to a charging and discharging node (7), and a second terminal connected to a pull-up node (6) for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node (7) is connected to the supply line (3) via a charging transistor (9) having a control terminal connected to a high-voltage bias node (11) formed by the adjacent stage in the opposite operating phase, for charging the capacitor (5) substantially up to the supply voltage.

公开(公告)号：DE69424771T2

公开(公告)日：2000-10-26

申请号：DE69424771

申请日：1994-03-22

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO ,  PADOAN SILVIA

IPC: G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28

Abstract: A device (20) including a load (27) connected by a selection circuit (4) to a number of bit lines (2), and a load (32, 33) connected to a reference cell (17), for detecting the current in the selected bit line (2) and in the reference cell. The load connected to the bit lines comprises a transistor (27), and the reference load comprises two current paths (32a, 33a), each formed by one transistor (32, 33). One (32) of the two transistors is diode-connected, and the other (33) is switchable by a switching network (35-50) connected to the gate terminal (34) of the respective transistor (33), for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

公开(公告)号：DE69424771D1

公开(公告)日：2000-07-06

申请号：DE69424771

申请日：1994-03-22

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO ,  PADOAN SILVIA

IPC: G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28

Abstract: A device (20) including a load (27) connected by a selection circuit (4) to a number of bit lines (2), and a load (32, 33) connected to a reference cell (17), for detecting the current in the selected bit line (2) and in the reference cell. The load connected to the bit lines comprises a transistor (27), and the reference load comprises two current paths (32a, 33a), each formed by one transistor (32, 33). One (32) of the two transistors is diode-connected, and the other (33) is switchable by a switching network (35-50) connected to the gate terminal (34) of the respective transistor (33), for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

公开(公告)号：DE69424764D1

公开(公告)日：2000-07-06

申请号：DE69424764

申请日：1994-01-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  PADOAN SILVIA

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H02M3/07 ,  G11C5/00

Abstract: A charge pump circuit (1) including a number of pull-up stages (2) connected in parallel with one another between a reference potential line (3) and an output line (4). Each stage (2) includes a capacitor (5) having a first terminal connected to a charging and discharging node (7), and a second terminal connected to a pull-up node (6) for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node (7) is connected to the supply line (3) via a charging transistor (9) having a control terminal connected to a high-voltage bias node (11) formed by the adjacent stage in the opposite operating phase, for charging the capacitor (5) substantially up to the supply voltage.

公开(公告)号：DE69328253D1

公开(公告)日：2000-05-04

申请号：DE69328253

申请日：1993-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA ,  PADOAN SILVIA

IPC: G11C5/14 ,  G11C16/06 ,  G11C17/00 ,  G11C16/30

Abstract: A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage (4) being powered between a first (VPP) and a second (GND) voltage reference and having a first input terminal connected to a resistive divider (2) of the first reference voltage (VPP) and an output terminal fed back to said input through a current mirror (3), and a source-follower transistor (MOUT) controlled by the output and connected to the cells through a programming line (VP). Also provided is a MOS transistor (MG2) which connects to ground the programming line (VP) and a corresponding resistive path (7) connected between the current mirror (3) and the second voltage reference (GND).

公开(公告)号：DE69326154T2

公开(公告)日：2000-02-24

申请号：DE69326154

申请日：1993-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G06F11/20

Abstract: An integrated circuit for the programming of a memory cell in a non-volatile memory register, said memory cell comprising at least one programmable non-volatile memory element (TF;TF0,TF1) having a cotrol electrode and a supply electrode and being suitable to store one bit of information and a load circuit (LC;T0-T3) associated to said memory element (TF;TF0,TF1) to read the information stored therein, comprises switching means (TS;T4,T5), connected in series between the supply electrode of said at least one memory element (TF;TF0,TF1) and a respective data line (A;A,AN) carrying a datum to be programmed into said memory element (TF;TF0,TF1); the switching means are controlled by a signal (7) which determines the switching means (TS;T4,T5) to electrically connect the memory element (TF;TF0,TF1) to the data line (A;A,AN) when the memory cell of the non-volatile memory register is to be programmed.

公开(公告)号：DE69328623T2

公开(公告)日：2001-02-08

申请号：DE69328623

申请日：1993-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PADOAN SILVIA ,  GOLLA CARLA

IPC: H01L27/04 ,  G05F3/24 ,  H01L21/822

公开(公告)号：DE69422794D1

公开(公告)日：2000-03-02

申请号：DE69422794

申请日：1994-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PADOAN SILVIA ,  PASCUCCI LUIGI

IPC: G11C17/00 ,  G11C16/06 ,  H01L27/10 ,  H03K19/177

Abstract: The PLA (1), which implements a state machine of a nonvolatile memory, presents a dynamic NAND-NOT-NOR configuration, and the timing signals for correct reading of the PLA are generated by a clock generator (30) which generates a monostable succession of read enabling signals (CPPA, CPPO, CPM) on receiving a predetermined switching edge of an external clock signal (CP). The clock generator enables evaluation of the AND (3) and OR (4) planes of the PLA and subsequently storage of the results through sections (33, 38; 48) duplicating the propagation delays of the signals in the corresponding parts (3-5) of the PLA. Reading is terminated as soon as completion of the storage step is indicated, so that reading of the PLA lasts only as long as strictly necessary, thus preventing erroneous switching while at the same time ensuring correct reading of the PLA.