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公开(公告)号：JP2675277B2
公开(公告)日：1997-11-12
申请号：JP8842895
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO
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公开(公告)号：JPH0896590A
公开(公告)日：1996-04-12
申请号：JP22351795
申请日：1995-08-31
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , PADOAN SILVIA , PASCUCCI LUIGI
Abstract: PROBLEM TO BE SOLVED: To lengthen a lifetime without applying useless stress to a beforehand programmed bit by re-programming only the cell of a bit incapable of being compared with data to be stored. SOLUTION: When the reference signal COMPRECH of a second input terminal 4 is at 'H', the No.i bit signal SOUTi of a 16 bit word read from the cell of a fresh memory is received by a first input terminal 3 through a sense amplifier SA in a comparator 2. When the second control signal DWE of a fourth input terminal 6 is at 'H', an input terminal 9 receives a bit value DBUFi corresponding to No.i cell from a latch holding data to be written to the memory. When the result of the comparison of the signals SOUTi and DBUFi is not correct, the signal DINCOMPi of a second output terminal 13 is at 'H', and a bit to be re-programmed is indicated. Accordingly, only the specified cell of a non-volatile memory is re-programmed.
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23.发明专利
公开(公告)号：JPH0856149A
公开(公告)日：1996-02-27
申请号：JP5377895
申请日：1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , PASCUCCI LUIGI
IPC: G11C17/00 , G11C16/06 , H01L27/10 , H03K19/177
Abstract: PURPOSE: To reduce an error in reading and to suppress power consumption by reading a programmable logic array for a memory only in a period necessitating reading. CONSTITUTION: PLA1 providing the state machine of a nonvolatile memory is provided with dynamic NAND-NOT-NOR constitution, a timing signal for correctly reading PLA is generated by a clock generator and this generator generates the monostable sequence of reading enabling signals CPPA, CPO and CPM on receiving a predetermined switching edge of an external clock signal CP. This clock generator enables evaluating the AND face 3 and the OR face 4 of PLA and continually enables storage of a result by parts 33, 38 and 48 reproducing the propagation delays of the signals at parts 3 to 5 PLA corresponds to. Reading is finished as soon as the storage step is completed to limit reading only in a necessary period.
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公开(公告)号：JPH0845282A
公开(公告)日：1996-02-16
申请号：JP8842895
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO
Abstract: PURPOSE: To realize high rate reading by providing a reference cell with additional current branches including a parallel transistor(TR) thereby setting the ratio between cell current and reference current higher at the time of equivalent step than at the time of evaluation step. CONSTITUTION: Bit line 5 and reference line 11 of a read circuit 1 are precharged with precharge circuits 4, 10 before an equivalent step and following evaluation step are carried out and the content stored in a cell 6 is read out through a sense amplifier 17. This circuit 1 is additionally provided with a current branch 31 comprising additional current TR 43, TR 44 having one end grounded through a line 11 and the other end grounded through a switching transistor 44 and the ratio between cell current and reference current on the lines 5, 11 is set higher at the time of equivalent step than at the time of evaluation step. Consequently, the current of a load means 8 is controlled quickly at the time of evaluation step and high rate reading is realized.
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公开(公告)号：JPH07254294A
公开(公告)日：1995-10-03
申请号：JP29488194
申请日：1994-11-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , PADOAN SILVIA
Abstract: PURPOSE: To provide an integrated circuit for programming memory cell in a non-volatile memory register while simplifying configuration and reducing the area to be occupied. CONSTITUTION: Concerning the integrated circuit for programming memory cell in the non-volatile memory register, a memory cell has a control electrode and a supply electrode, and one programmable non-volatile memory cell TF suitable for storing the information of one bit at least and a load circuit LC for reading the information stored in this memory cell are provided. The integrated circuit is provided with a switching means TS serially connected between the supply electrode of the memory cell TF and each data line A for conveying data to be programmed into the memory cell. When programming the memory cell in the non-volatile memory register, this switching means is controlled by a signal 7 for electrically connecting the memory cell TF to the data line A. The data line A is defined as the address signal line of an address signal bus to be used for the decoder circuit of memory matrix as well.
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Patent Agency Ranking26.发明专利
公开(公告)号：JPH076592A
公开(公告)日：1995-01-10
申请号：JP14491092
申请日：1992-05-11
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
Abstract: PURPOSE: To provide a modulating current offset type or a current offset type sense amplifier having excellent insensitivity to a noise, a high speed, high reliability and a small number of elements. CONSTITUTION: The same loads TLM and TLR in two lines are crossly coupled, form the loads of differential input transistor pairs TDM, TDR of a differential sense amplifier and form a latch for storing data extracted during the last phase of a read-out cycle together with the input transistor pairs. By this constitution, the particular cross-coupled connection of loads TLM, TLR gives positive feedback for improving amplifying ability to the sense amplifier not requiring other amplifying stage.
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公开(公告)号：JPH06342596A
公开(公告)日：1994-12-13
申请号：JP22458792
申请日：1992-07-31
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , OLIVO MARCO
IPC: G11C11/417 , G11C7/10 , G11C7/14 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/409 , G11C11/413
Abstract: PURPOSE: To prevent noise from generating from an output switching and not to produce an error in read data by providing a transition detection circuit and a dummy chain block. CONSTITUTION: A dummy chain block consists of a dummy DEC (D-DEC), a dummy memory matrix D-WL and a dummy sense amplifier D-SA circuit block. A transition detection circuit ATD detects signal transition from an input and a control circuit ADD-BUFF, generates its pulse and makes a dummy chain DWL which reproduces transmission delay of a signal that passes through a matrix WLi of a memory cell usable by means of a reset signal. Then, it transfers a generation pulse through the dummy chain DWL which is made to be usable, generates a 2nd pulse which can make an extract data output storage circuit OL usable and makes the dummy chain DWL which is made to be usable unusable.
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公开(公告)号：JPH06282993A
公开(公告)日：1994-10-07
申请号：JP21857892
申请日：1992-07-25
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , OLIVO MARCO
IPC: G11C11/417 , G11C7/06 , G11C16/06 , G11C16/28 , G11C17/00
Abstract: PURPOSE: To increase the level of differential output by functionally connecting the output nodes of two control circuits to the respective sources of respective transistors for differential amplification. CONSTITUTION: As p-channel transistors TLR and TLM, load elements are cross- coupled and constitutes an output latch circuit for storing the extraction information of representative signals existent across output nodes OUTR and OUTM of sense amplifier together with input transistors TDR and TDM of differential amplifier. A timing signal ϕEN is inputted to one of respective control circuits. The other input is coincident with input nodes INM and INR of sense differential amplifier between the transistors TLM and TLR and lines MBL and RBL. The circuit is completed by equalizing transistors functionally connected across an evaluation bit line TES and transistors TEC and TEL across output nodes CM and CR.
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公开(公告)号：JPH05303899A
公开(公告)日：1993-11-16
申请号：JP25585892
申请日：1992-08-31
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
Abstract: PURPOSE: To form an independent drive circuit and to prevent deterioration in performance by using a structure, based on four pieces of respective selectors for performing required two level decoding. CONSTITUTION: An imparted block of a cell is selected by switching an answering signal from a G bus to an L level. When a piece of wire of a P bus is in an H level, the answering circuit node G of the block of the selected cell is made grounded potential by a bus FET-Tp. Only a piece of selection line of a first coding level is decoded by unequivocal first decoding level selection performed through Ts answering to an S bus, and a certain division of the cells of the block is selected, and the specified cell addressed for read-out among the cells is decided. Simultaneously, a Q bus of two pieces of wires preliminarily selects a selection driver of a group of 16 pieces of rows through answering Tq0 and Tq1 .
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公开(公告)号：DE60141200D1
公开(公告)日：2010-03-18
申请号：DE60141200
申请日：2001-05-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
Abstract: A memory system (1000) comprises a memory matrix (110) formed on a semiconductor structure, the memory matrix including: a first column line (BC-4) and a second column line (BC-5) which are connected electrically to at least one first memory cell (Q65) to be read, for the reading of the at least one first cell (Q65) a first reading voltage can be supplied to the first column line (BC-4), and a third column line (BC-1) distinct from the first column line (BC-4) and from the second column line (BC-5), and is characterized in that it further comprises generating means (SCR) for supplying, to the third column line (BC-1) and during the reading of the at least one first memory cell (Q65), a biasing voltage which can oppose the establishment of an electric current between the first column line (BC-4) and the third column line (BC-1) in the semiconductor structure. The biasing voltage is preferably substantially equal to the first reading voltage.
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