公开(公告)号：DE69515876D1

公开(公告)日：2000-04-27

申请号：DE69515876

申请日：1995-11-06

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE ,  RINAUDO SALVATORE

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/78

公开(公告)号：DE69418037T2

公开(公告)日：1999-08-26

申请号：DE69418037

申请日：1994-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L21/60 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L29/72

Abstract: In a MOS-technology power device chip and package assembly, the MOS-technology power device chip (1) comprises a semiconductor material layer (4,5) in which a plurality of elementary functional units (6) is integrated, each elementary functional unit (6) contributing for a respective fraction to an overall current and comprising a first doped region (7) of a first conductivity type formed in said semiconductor layer (4,5), and a second doped region (10) of a second conductivity type formed inside said first doped region (7); the package (2) comprises a plurality of pins (P1-P10) for the external electrical and mechanical connection; said plurality of elementary functional units (6) is composed of sub-pluralities of elementary functional units (6), the second doped regions (10) of all the elementary functional units (6) of each sub-plurality being contacted by a same respective metal plate (100) electrically insulated from the metal plates (100) contacting the second doped regions (10) of all the elementary functional units (6) of the other sub-pluralities; each of said metal plate (100) is connected, through a respective bonding wire (W1-W5), to a respective pin (P1-P5) of the package (2).

公开(公告)号：DE69534919T2

公开(公告)日：2007-01-25

申请号：DE69534919

申请日：1995-10-30

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  MAGRI ANGELO ,  FERLA GIUSEPPE

IPC: H01L29/06 ,  H01L29/74 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

Abstract: A MOS technology power device comprises: a semiconductor material layer (2) of a first conductivity type; a conductive insulated gate layer (7,8,9) covering the semiconductor material layer (2); a plurality of elementary functional units, each elementary functional unit comprising a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of an elongated body stripe, each elementary functional unit further comprising an elongated window (12) in the insulated gate layer (7,8,9) extending above the elongated body stripe (3). Each body stripe (3) includes at least one source portion (60;61;62) doped with dopants of the first conductivity type, intercalated with a body portion (40;41;3') of the body stripe (3) wherein no dopant of the first conductivity type are provided. The conductive insulated gate layer (7,8,9) comprises a first insulating material layer (7) placed above the semiconductor material layer (2), a conductive material layer (8) placed above the first insulating material layer (7), and a second insulating material layer (9) placed above the conductive material layer (8). Insulating material sidewall spacers (13) are provided to seal edges of the elongated window (12) in the insulated gate layer (7,8,9).

公开(公告)号：DE69434268D1

公开(公告)日：2005-03-17

申请号：DE69434268

申请日：1994-07-14

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

Abstract: A high-speed MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a lightly doped semiconductor layer (1) of a first conductivity type, the elementary functional units comprising channel regions (6) of a second conductivity type covered by a conductive insulated gate layer (8) comprising a polysilicon layer (5); the conductive insulated gate layer (8) also comprises a highly conductive layer (9) superimposed over said polysilicon (5) layer and having a resistivity much lower than the resistivity of the polysilicon layer (5), so that a resistance introduced by the polysilicon layer (5) is shunted with a resistance introduced by said highly conductive layer (9) and the overall resistivity of the conductive insulated gate (8) layer is lowered.

公开(公告)号：DE69428894T2

公开(公告)日：2002-04-25

申请号：DE69428894

申请日：1994-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L29/739

Abstract: A power device integrated structure comprises a semiconductor substrate (5) of a first conductivity type, a semiconductor layer (3,4) of a second conductivity type superimposed over said substrate (5), a plurality of first doped regions (2) of the first conductivity type formed in the semiconductor layer (3,4), and a respective plurality of second doped regions (11) of the second conductivity type formed inside the first doped regions (2); the power device comprises: a power MOSFET (M) having a first electrode region represented by the second doped regions (11) and a second electrode region represented by the semiconductor layer (3,4); a first bipolar junction transistor (T2) having an emitter, a base and a collector respectively represented by the substrate (5), the semiconductor layer (3,4) and the first doped regions (2); and a second bipolar junction transistor (T1) having an emitter, a base and a collector respectively represented by the second doped regions (11), the first doped regions (2) and the semiconductor layer (3,4); the doping profiles of the semiconductor substrate (5), the semiconductor layer (3,4), the first doped regions (2) and the second doped regions (11) are such that the first and second bipolar junction transistors (T2,T1) have respective first and second common base current gains sufficiently high to cause said bipolar junction transistors to be biased in the high injection region, so that carriers are injected from the substrate (5) into the semiconductor layer (3,4) and from the second doped regions (11), through the first doped regions (2), into the semiconductor layer (3,4), the conductivity of the semiconductor layer (3,4) is thus modulated not only by the injection of minority carriers from the substrate (5), but also by majority carriers injected from the doped regions (11) into the first doped regions (2) and collected by the semiconductor layer (3,4). The first and second common base current gains summed are less than unity to prevent a parasitic thyristor from triggering on. The power device functions as an IGBT, having a reduced on-state voltage.

公开(公告)号：DE69523576D1

公开(公告)日：2001-12-06

申请号：DE69523576

申请日：1995-06-16

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： SANTANGELO ANTONELLO ,  FERLA GIUSEPPE

IPC: H01L21/331 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78 ,  H01L23/00 ,  H01L29/43

Abstract: An electronic semiconductor device (20) with a control electrode (19) consisting of self-aligned polycrystalline silicon (4) and silicide (12), of the type in which said control electrode (19) is formed above a portion (1) of semiconductor material which accommodates active areas (9) of the device (20) laterally with respect to the electrode, has the active areas (9) at least partially protected by an oxide layer (10) while the silicide layer (12) is obtained by means of direct reaction between a metal film deposited on the polycrystalline silicon (4) and on the oxide layer (10).

公开(公告)号：DE69229927T2

公开(公告)日：2000-01-20

申请号：DE69229927

申请日：1992-03-17

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO FRISINA FERR ,  FERLA GIUSEPPE

IPC: H01L21/22 ,  H01L21/322 ,  H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/732 ,  H01L29/861

Abstract: The structure consists of a single chip (1) of semiconductor material, which comprises an area (32) having a high lifetime of the minority carriers, which constitutes a bipolar power device with high current density, and at least one area (20, 21; 20', 21') with a reduced lifetime of the minority carriers, which constitutes a fast diode.

公开(公告)号：JPH09298301A

公开(公告)日：1997-11-18

申请号：JP28872996

申请日：1996-10-30

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  MAGRI ANGELO ,  FERLA GIUSEPPE

IPC: H01L29/74 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/749 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a power device with a higher integration scale than a conventional MOS technique power device. SOLUTION: This device is provided with a conductive insulating gate layer covering a first conductivity type semiconductor layer and a plurality of basic function unit. Each basic function unit contains a slim window formed on an insulating gate layer 9 extending on a slim base body 3. The first conductivity type source regions 60 not doped with impurities of the main parts 40 are alternately positioned in each slim base body 3. Further, a side wall spacer of an insulating material is formed along a longitudinally directed edge of each slim window so as to seal an edge of each slim window. A source metal layer is brought into contact with each slim main body region and each source region through each main body region.

公开(公告)号：JPH09252115A

公开(公告)日：1997-09-22

申请号：JP28875896

申请日：1996-10-30

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To make the contact of source metal layers and main body areas satisfactory even if scaled down to the limit of photolithography and to realize high integration. SOLUTION: Respective basic function unit contain second conductive long main body areas 3 being parallel bars which are formed in a semiconductor material layer and are detached by the distance (d). Main body parts 40 to which first conductive impurities are not given and first conductive source areas 60 are mutually positioned in the respective long main body areas 3. Openings 11 are provided for dielectric layers 9 sealing the conductive layers to be grown to gates along the center parts of the long main body areas 3. The metal layers constituting a source electrode are brought into contact with the source areas 60 and the main body parts 40.

公开(公告)号：JPH04215424A

公开(公告)日：1992-08-06

申请号：JP4555091

申请日：1991-02-20

Applicant: ST MICROELECTRONICS SRL

Inventor： SANTANGELO ANTONELLO ,  MAGRO CARMELO ,  FERLA GIUSEPPE ,  LANZA PAOLO

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/329 ,  H01L21/768

Abstract: PURPOSE: To form the M-S contact of ohmic characteristic on a small doping region through dopant enrichment treatment on a contact surface by keeping the temperature and time of annealing treatment, which is to be performed after ion implantation on the surface of a semiconductor, at values without the possibility of changing functional characteristics in the structure of a device on the front surface of a wafer. CONSTITUTION: As a metal semiconductor ohmic contact forming treatment, the ion implantation of dopant is performed on the surface of a semiconductor 1. Next, a metal film 4 is deposited on the surface, where the ion implantation is performed, and then annealing treatment is performed considerably shorter than 60 minutes at a temperature considerably lower than 500 deg.C, so that dopant enrichment can be performed on the surface of the semiconductor 1 for forming the contact.