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    21.
    发明专利
    未知

    公开(公告)号：DE69533134T2

    公开(公告)日：2005-07-07

    申请号：DE69533134

    申请日：1995-10-30

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739

    Abstract: A MOS technology power device comprises a plurality of elementary functional units which contribute for respective fractions to an overall current of the power device and which are formed in a semiconductor material layer (2) of a first conductivity type. Each elementary functional unit comprises a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of a body stripe (3) elongated in a longitudinal direction on a surface of the semiconductor material layer (2). Each body stripe (3) includes at least one source portion (60) doped with dopants of the first conductivity type which is intercalated with a body portion (40) of the body stripe (3) wherein no dopants of the first conductivity type are provided.

    MOS TECHNOLOGY POWER DEVICE
    25.
    发明专利
    MOS TECHNOLOGY POWER DEVICE 失效

    公开(公告)号：JPH09252115A

    公开(公告)日：1997-09-22

    申请号：JP28875896

    申请日：1996-10-30

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To make the contact of source metal layers and main body areas satisfactory even if scaled down to the limit of photolithography and to realize high integration. SOLUTION: Respective basic function unit contain second conductive long main body areas 3 being parallel bars which are formed in a semiconductor material layer and are detached by the distance (d). Main body parts 40 to which first conductive impurities are not given and first conductive source areas 60 are mutually positioned in the respective long main body areas 3. Openings 11 are provided for dielectric layers 9 sealing the conductive layers to be grown to gates along the center parts of the long main body areas 3. The metal layers constituting a source electrode are brought into contact with the source areas 60 and the main body parts 40.

    MOS TECHNIQUE POWER DEVICE
    26.
    发明专利
    MOS TECHNIQUE POWER DEVICE 失效

    公开(公告)号：JPH09298301A

    公开(公告)日：1997-11-18

    申请号：JP28872996

    申请日：1996-10-30

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： FRISINA FERRUCCIO ,  MAGRI ANGELO ,  FERLA GIUSEPPE

    IPC: H01L29/74 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/749 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a power device with a higher integration scale than a conventional MOS technique power device. SOLUTION: This device is provided with a conductive insulating gate layer covering a first conductivity type semiconductor layer and a plurality of basic function unit. Each basic function unit contains a slim window formed on an insulating gate layer 9 extending on a slim base body 3. The first conductivity type source regions 60 not doped with impurities of the main parts 40 are alternately positioned in each slim base body 3. Further, a side wall spacer of an insulating material is formed along a longitudinally directed edge of each slim window so as to seal an edge of each slim window. A source metal layer is brought into contact with each slim main body region and each source region through each main body region.

    STRUCTURE METHOD FOR ELECTRIC POWER DEVICE
    27.
    发明专利
    STRUCTURE METHOD FOR ELECTRIC POWER DEVICE 失效

    公开(公告)号：JPH09129722A

    公开(公告)日：1997-05-16

    申请号：JP26699796

    申请日：1996-10-08

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： FRANCO GIOVANNI ,  CAMALLERI CATENO MARCO ,  FRISINA FERRUCCIO

    IPC: H01L21/761 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06

    Abstract: PROBLEM TO BE SOLVED: To provide an electric power device wherein high yield efficiency is obtained with low ion implantation energy and provided with a deep edge ring by, with the use of a boron and Al as a dopant, forming a deep ring at the same time for the main body of a device in a single thermal process, and further, an oxide layer used during Al ion implantation. SOLUTION: On a heavily doped N type substrate 10, a slightly doped N type epitaxial layer 20 is grown, further, over the upper part of the epitaxial layer 20, an oxide 30 is grown. By photo-etching, an main body is exposed itself in an area 30, and boron 40 is implanted for a p are 42 to be generated. Then, oxide etching is performed, the area for Al ion implantation is made exposed, thus an Al ring is configured. By masking the main body area with a photosensitive material layer, an Al ion 60 is implanted. Then, through a single thermal diffusion process, P /N joint 80 formed through formation of a thermal oxide layer 70 and boron, and one or more P /N joints 90 formed by Al are formed at the same time.

    28.
    发明专利
    未知

    公开(公告)号：DE69324003T2

    公开(公告)日：1999-07-15

    申请号：DE69324003

    申请日：1993-06-28

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： FRISINA FERRUCCIO ,  COFFA SALVATORE

    IPC: H01L21/331 ,  H01L29/06 ,  H01L29/167 ,  H01L29/73 ,  H01L29/732

    Abstract: There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate (1) of the N type over which a lightly doped N type layer (2), constituting a collector region of the transistor, is superimposed; the transistor has a base region comprising a heavily doped P type diffusion (4) which extends into the lightly doped N type layer (2) from a top surface, and an emitter region constituted by a heavily doped N type diffusion (11) extending from said top surface within said heavily doped P type diffusion (4); the heavily doped P type diffusion (4) is obtained within a deep lightly doped P type diffusion (3), extending from said top surface into the lightly doped N type layer (2) and formed with acceptor impurities represented by atoms of aluminium.

    29.
    发明专利
    未知

    公开(公告)号：DE69321966D1

    公开(公告)日：1998-12-10

    申请号：DE69321966

    申请日：1993-12-24

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： FRISINA FERRUCCIO ,  MANGIAGLI MARCANTONIO

    IPC: H01L27/04 ,  H01L21/60 ,  H01L21/822 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78 ,  H01L27/105

    Abstract: An integrated structure pad assembly for lead bonding to a power semiconductor device chip comprises a chip portion having a top surface covered by a metallization layer (10) and which comprises a first sub-portion (1) wherein functionally active elements of the power device are present; said chip portion comprises at least one second sub-portion (11) wherein no functionally active elements of the power device are present, and a top surface of the metallization layer (10) is elevated over said at least one second sub-portion (11) with respect to the first sub-portion (1) to form at least one protrusion which forms a support surface for a lead.

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