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    24.
    发明专利
    未知

    公开(公告)号：IT9006609D0

    公开(公告)日：1990-04-20

    申请号：IT660990

    申请日：1990-04-20

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： ZAMBRANO RAFFAELE

    IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/78 ,  H01L

    Abstract: The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage in comparison with known structures by provision of one or more regions of high dopant concentration defined after growth of a first epitaxial layer.

    26.
    发明专利
    未知

    公开(公告)号：DE69327320D1

    公开(公告)日：2000-01-20

    申请号：DE69327320

    申请日：1993-09-30

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： ZAMBRANO RAFFAELE

    IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78

    Abstract: An integrated structure active clamp for the protection of a power device against overvoltages comprises a plurality of serially connected diodes (D1-D4,SD1-D4,DF1,DF2), each having a first and a second electrodes, obtained in a lightly doped epitaxial layer (2;2,2') of a first conductivity type in which the power device (M) is also obtained; a first diode (D1;SD1) of said plurality of diodes has the first electrode (12,13;31,32) connected to a gate layer (7) of the power device (M) and the second electrode (14,15;35) connected to the second electrode (16,17;21,22;27,52,28) of at least one second diode (D2-D4) of the plurality whose first electrode (18,20,24,29) is connected to a drain region (D) of the power device (M); said first diode (D1;SD1) has its first electrode (12,13;31,32) comprising a heavily doped contact region (12;32) of the first conductivity type included in a lightly doped epitaxial layer region (13;31) of the first conductivity type which is isolated from said lightly doped epitaxial layer (2;2,2') by means of a buried region (14;33) of a second conductivity type and by a heavily doped annular region (15;34) of the second conductivity type extending from a semiconductor top surface to said buried region (14;33).

    27.
    发明专利
    未知

    公开(公告)号：DE69029942T2

    公开(公告)日：1997-08-28

    申请号：DE69029942

    申请日：1990-10-16

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： ZAMBRANO RAFFAELE ,  MAGRO CARMELO

    IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/772

    Abstract: The process provides first for the accomplishment of low-doping body regions (12) at the sides and under a gate region (15) and then the accomplishment of high-doping body regions (14) inside said low-doping body regions (12) and self-aligned with said gate region (15). There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions (14) self-aligned with said gate region (15) and with a reduced junction depth.

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