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公开(公告)号：JPH0883494A
公开(公告)日：1996-03-26
申请号：JP5377795
申请日：1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: PURPOSE: To obtain a timer which can be constituted by a slow element excellent in noise characteristics. CONSTITUTION: This embodiment is a nonvolatile memory 100 comprising a data amplifier 106 and an output element 108 connecting with each other via a connection line 107. A noise suppression circuit 1 comprises networks 8, 18 for generating a noise suppression signal N which is synchronized completely with a signal L for controlling a data loading from the amplifier 106 to the output device 108. A very short lasting time period same as a switch time period of the output device 108 is given, and when the output device 108 is switched, the amplifier 106 is frozen, and data stored in the amplifier or an internal circuit of the memory 100 cannot be changed. An address amplifier 102 on address buses 101, 103 is blockaded according to the same signal.
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公开(公告)号：JPH0847246A
公开(公告)日：1996-02-16
申请号：JP1306395
申请日：1995-01-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , MACCARRONE MARCO , PADOAN SILVIA
Abstract: PURPOSE: To supply large power in the case that an input/output voltage ratio is low or a power supply voltage is low by mutually connecting in parallel pull-up stages between a reference potential line and an output line. CONSTITUTION: This charge pump circuit 1 is provided with numerous stages 21 -2n connected in parallel to each other between the reference potential line 3 and the output line 4, the respective stages 21 -2n are provided with bootstrap capacitors 51 -5n , the one side is connected to nodes 71 -7n and the other terminals are connected to nodes 61 -6n . Then, when inverters 121 -12n are switched, the odd-numbered stages 21 , 23 ,... are switched to a charge transfer mode, the even- numbered stages are switched to a charging mode. When a switching edge reaches a stage 2n-1 which is one next to the last, an AND circuit 15 and a NOR circuit 16 are switched, shifting along the inverters 121 -12n is performed, the odd-numbered stages 21 , 23 ,... are charged, and the even-numbered stages 22 , 24 ,... transfer the stored charges. As a result, even in the case that an input voltage ratio is low, voltage is efficiently boosted and a large power is supplied.
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公开(公告)号：JPH0845289A
公开(公告)日：1996-02-16
申请号：JP5377695
申请日：1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , MACCARRONE MARCO , OLIVO MARCO
Abstract: PURPOSE: To set a timing accurately while suppressing noise by loading a simulate signal to an output simulation circuit through a switch subjected to required control and resetting a simulate generation circuit in response to the variation of simulate signal. CONSTITUTION: Upon provision of a sync signal SYNC, a simulate signal SP is generated from the simulate signal generator 34 of delay FF and a load block signal SS makes a transition to L through a switch 35 opened by a load enable signal L before being loaded to an unblocked output simulation circuit 21. When the signal SP is inverted to 'L', output is inverted to H through a NAND gate 30 and an inverter 32 and the generator 34 is reset instantaneously through a monostable multivibrator 33. On the other hand, a signal SS is inverted to H and loading to the circuit 21 is blocked. According to the circuitry, loading of signal and blocking of loading are controlled accurately and the effect of noise due to housing is suppressed.
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公开(公告)号：JPH07262792A
公开(公告)日：1995-10-13
申请号：JP30221994
申请日：1994-12-06
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA
Abstract: PURPOSE: To reduce a chip area by unnecessitating any protection memory cell by forming a combined circuit for generating a signal for inhibiting the selection of any memory cell. CONSTITUTION: A non-volatile register 1 is formed from memory cells MC0-MCn and a redundant word line selection circuit 2. The cells MC0-MCn have output signals CMP0-CMPn to be activated when row address signals are coincident with memories. The selection circuit 2 inputs all the signals CM0-CMPn and generates signals RS0-RSi for selecting any one redundant line word and preventing the defective word line of which the address is coincident with the address stored in the register from being selected. Besides, a combined circuit 3 generates a signal DIS for inhibiting the selection circuit 2 from generating the signals RS0-RSi. The protection memory cell is unnecessitated by a redundant circuit formed from the selection circuit 2 and the combined circuit 3.
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公开(公告)号：JPH07254296A
公开(公告)日：1995-10-03
申请号：JP30490094
申请日：1994-12-08
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , MACCARRONE MARCO
Abstract: PURPOSE: To provide an integrated circuit for checking the use rate of a redundant memory element inside a semiconductor memory device. CONSTITUTION: A redundant circuit is provided with a programmable nonvolatile memory register 1 for respectively storing the addresses of defective memory elements. When the stored address is coincident with supplied address signals A0-An, a redundant select signal RS is generated. Besides, the signals A0-A1 are supplied to combined circuit means 3 and 9 of the redundant circuit and when a suppress signal DIS' is supplied to the register 1 and the signals A0-An are coincident with the addresses stored in the non-programmed register 1, the generation of the redundant select signal RS is suppressed. When a control signal CHKN is activated, a multiplexer circuit means 11 under the control of the signal CHKN transmits the signal RS to and output pad 17 and when the generation of the signal DIS' is activated, the signal CHKN disturbs that generation.
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Patent Agency Ranking
公开(公告)号：JPH06325592A
公开(公告)日：1994-11-25
申请号：JP5878794
申请日：1994-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： OLIVO MARCO , PASCUCCI LUIGI
Abstract: PURPOSE: To unnecessitate a specified load circuit to program cells in a redundancy row by positioning at an intersection a line and a row of matrix itself and providing matrix consisting of memory cells. CONSTITUTION: A load circuit 3 for programming is connected to a common drain of transistors MS and MSR of each bucket 1. The circuit 3 consists of P channel MOS type transistor MP1, its drain is connected to the common drain of the transistors MS and MSR, its source is connected to programming voltage VP and its gate is connected to an input of a circuit 4 which has a NAND logic function. The circuit 4 is provided with a P channel MOS type load transistor M41, its source and drain are respectively connected to the voltage VP and a gate of the MP1 and make them ground electric potential. A drain of a transistor M42 is connected to a drain of the transistor M41, a drain of a transistor M43 is connected to its source, the source is ground electric potential and signals YMO to YM7 are given here. Thus, a signal DIN to program is acquired.
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公开(公告)号：JP2675277B2
公开(公告)日：1997-11-12
申请号：JP8842895
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO
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公开(公告)号：JPH0896590A
公开(公告)日：1996-04-12
申请号：JP22351795
申请日：1995-08-31
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , PADOAN SILVIA , PASCUCCI LUIGI
Abstract: PROBLEM TO BE SOLVED: To lengthen a lifetime without applying useless stress to a beforehand programmed bit by re-programming only the cell of a bit incapable of being compared with data to be stored. SOLUTION: When the reference signal COMPRECH of a second input terminal 4 is at 'H', the No.i bit signal SOUTi of a 16 bit word read from the cell of a fresh memory is received by a first input terminal 3 through a sense amplifier SA in a comparator 2. When the second control signal DWE of a fourth input terminal 6 is at 'H', an input terminal 9 receives a bit value DBUFi corresponding to No.i cell from a latch holding data to be written to the memory. When the result of the comparison of the signals SOUTi and DBUFi is not correct, the signal DINCOMPi of a second output terminal 13 is at 'H', and a bit to be re-programmed is indicated. Accordingly, only the specified cell of a non-volatile memory is re-programmed.
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29.发明专利
公开(公告)号：JPH0856149A
公开(公告)日：1996-02-27
申请号：JP5377895
申请日：1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： PADOAN SILVIA , PASCUCCI LUIGI
IPC: G11C17/00 , G11C16/06 , H01L27/10 , H03K19/177
Abstract: PURPOSE: To reduce an error in reading and to suppress power consumption by reading a programmable logic array for a memory only in a period necessitating reading. CONSTITUTION: PLA1 providing the state machine of a nonvolatile memory is provided with dynamic NAND-NOT-NOR constitution, a timing signal for correctly reading PLA is generated by a clock generator and this generator generates the monostable sequence of reading enabling signals CPPA, CPO and CPM on receiving a predetermined switching edge of an external clock signal CP. This clock generator enables evaluating the AND face 3 and the OR face 4 of PLA and continually enables storage of a result by parts 33, 38 and 48 reproducing the propagation delays of the signals at parts 3 to 5 PLA corresponds to. Reading is finished as soon as the storage step is completed to limit reading only in a necessary period.
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公开(公告)号：JPH0845282A
公开(公告)日：1996-02-16
申请号：JP8842895
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO
Abstract: PURPOSE: To realize high rate reading by providing a reference cell with additional current branches including a parallel transistor(TR) thereby setting the ratio between cell current and reference current higher at the time of equivalent step than at the time of evaluation step. CONSTITUTION: Bit line 5 and reference line 11 of a read circuit 1 are precharged with precharge circuits 4, 10 before an equivalent step and following evaluation step are carried out and the content stored in a cell 6 is read out through a sense amplifier 17. This circuit 1 is additionally provided with a current branch 31 comprising additional current TR 43, TR 44 having one end grounded through a line 11 and the other end grounded through a switching transistor 44 and the ratio between cell current and reference current on the lines 5, 11 is set higher at the time of equivalent step than at the time of evaluation step. Consequently, the current of a load means 8 is controlled quickly at the time of evaluation step and high rate reading is realized.
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