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    High-precision calibration circuit calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance
    26.
    发明公开
    High-precision calibration circuit calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance 有权
    用于校准集成电路的可调电容的时间常数依赖于电容高精度校准电路

    公开(公告)号：EP1962420A1

    公开(公告)日：2008-08-27

    申请号：EP07425099.4

    申请日：2007-02-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Nicollini, Germano

    IPC: H03H1/02 ,  H03H7/01

    CPC classification number: H03H7/0153 ,  H03H1/02 ,  H03H2210/021 ,  H03H2210/043

    Abstract: A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitance ((C var (REG_BUS)) and including a calibration loop (U_CV, CMP, TG_SAR), suitable to carry out a calibration cycle (C_LOOP) in several sequential steps (St_1, ..., St4), comprising:
    - a controllable capacitance unit (U_CV) suitable to receive a control signal (SAR_BUS) at the beginning of a calibration step and including an array of switched capacitors (C_AR1) that can be selectively activated by the control signal to be connected to a first common node (N_u) having, at the end of an integration interval (P2), a voltage value (VRC) depending on the total capacitance value of the activated capacitors;
    - an assessment unit (CMP) suitable to compare this voltage value (VRC) with a reference voltage to output a logic signal (OUT_CMP) that, based on the comparison result can be subjected to a transition between first and second logic levels;
    - a control and timing unit (TG_SAR) suitable to receive the logic signal (OUT_CMP) and to change the control signal (SAR_BUS) based thereon, in order to carry out a subsequent calibration step,

    characterized in that
    in said calibration step is provided, at the end of said integration interval (P2) a comparison interval (P3) of a preset duration, which allows a transition (tl,t4) of the logic signal (OUT_CMP) to occur prior to the beginning of said consecutive calibration step.

    Abstract translation: 用于校准（在具有时间常数取决于所述可调电容的电路（31）的可调节的电容（C VAR（REG_BUS））的校准电路（30），所述校准电路（30）被检查，以输出一个校准信号REG_BUS ）携带信息用于校准所述电容（C（VAR（REG_BUS））和包括校准环路（U_CV，CMP，TG_SAR），适合在几个连续的步骤来进行校准周期（C_LOOP）（ST_1，...，圣4 ），包括： - 一个可控电容单元（U_CV）适合于在校准步骤的开始接收的控制信号（SAR_BUS），并在开关电容器阵列（C_AR1）包括也可以由控制信号被选择性地激活以连接 到第一公共节点（N_u），其具有，在一个积分区间（P2）结束时，一个电压值（VRC）根据激活的电容器的总电容值; - 评估单元（CMP）适合于比较该电压 值（VRC）与参考 ENCE电压以输出逻辑信号（OUT_CMP），基于该比较结果可以进行第一和第二逻辑电平之间的转变; - 控制和定时单元（TG_SAR）适合于接收所述逻辑信号（OUT_CMP）和改变控制信号（SAR_BUS）基于其，以便进行随后的校准步骤中，在“那个”中设置的所述校准步骤为特征的， 在逻辑信号（OUT_CMP）的所述积分间隔（P2）在预设持续时间的比较区间（P3），它允许一个过渡（TL，T4）的端部之前，所述连续校准步骤的开始时发生。

    Analog digital converter
    27.
    发明公开
    Analog digital converter 有权
    模拟数字Wandler

    公开(公告)号：EP1887702A1

    公开(公告)日：2008-02-13

    申请号：EP06425570.6

    申请日：2006-08-04

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

    IPC: H03M1/46 ,  H03M1/06

    CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

    Abstract: An analog digital converter (41) for converting an analog signal (V INP ,V INM ) into a digital output code (D OUT ), comprising:
    - a local digital analog converter (42) including at least one segmented array (AR P ,AR M ) comprising an upper segment (AR UP ,AR UM ) and a lower segment (AR LP ,AR LM ) of conversion elements selectively operable by means of respective command codes (CMD COD ) for varying, according to binary weighted contributions, the voltage of a first common node (NS UP ,NS UM ) and the voltage of a second common node (NS LP ,NS LM ) respectively,
    - a logic unit (3) to generate digital command codes (CMD COD ) so as to control the local digital/analog converter (42) according to the successive approximation technique for producing the digital output code (D OUT ).
    The converter (41) includes redistribution means (46) such as to modify the command codes for redistributing the command codes between the lower segment and the upper segment, making use of at least one auxiliary conversion element (C U1 ,C U2 ) provided in the upper segment.

    Abstract translation: 一种用于将模拟信号（V INP，V INM）转换为数字输出代码（D OUT）的模拟数字转换器（41），包括： - 本地数字模拟转换器（42），包括至少一个分段阵列（AR P， AR M）包括通过相应的命令码（CMD COD）选择性地操作的转换元件的上段（AR UP，AR UM）和下段（AR LP，AR LM），用于根据二进制加权贡献来改变 第一公共节点（NS UP，NS UM）的电压和第二公共节点（NS LP，NS LM）的电压分别为产生数字命令码（CMD COD）以便控制的逻辑单元（3） 本地数字/模拟转换器（42）根据用于产生数字输出代码（D OUT）的逐次逼近技术。 转换器（41）包括再分配装置（46），以便利用至少一个辅助转换元件（C U1，C U2）修改用于在下部段和上部段之间重新分配命令代码的命令代码 上段。

    Class-D audio amplifier
    29.
    发明公开
    Class-D audio amplifier 审中-公开
    Klasse-DAudioverstärker

    公开(公告)号：EP1788701A1

    公开(公告)日：2007-05-23

    申请号：EP05425811.6

    申请日：2005-11-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Guanziroli, Federico ,  Nicollini, Germano ,  Confalonieri, Pierangelo

    IPC: H03F3/217

    CPC classification number: H03F3/217 ,  H03F3/2173 ,  H03F2200/78

    Abstract: An open-loop class-D amplifier (300) comprises a generation device (307) of a triangular wave signal (v tri (t)) having a differential output. Furthermore, the amplifier comprises at least one comparing circuit (302) provided with first differential input terminals (S+,S-) in order to receive a first signal (v in (t)) and second differential input terminals (T+,T-) in order to receive the triangular signal.
    In addition, the amplifier comprises a power stage (300') in order to give an output signal (v out (t)) to a load (306) and a terminal connectable to a power supply potential (V A ).
    The amplifier is characterized in that the generation device is such that the triangular signal has a peak value (V tri ) which is substantially proportional to said power supply potential (V A ) and a frequency (f fri ) which is fixed to a reference frequency value (f ck ), for the power supply potential changes.

    Abstract translation: 开环D类放大器（300）包括具有差分输出的三角波信号（v tri（t））的生成装置（307）。 此外，放大器包括至少一个比较电路（302），用于接收第一信号（v in（t））和第二差分输入端子（T +，T）中的第一差分输入端子（S +，S-） 以便接收三角形信号。 此外，放大器包括功率级（300'），以便给出负载（306）的输出信号（v out（t））和可连接到电源电位（V A）的端子。 所述放大器的特征在于，所述发生装置使得所述三角形信号具有与所述电源电位（VA）基本成比例的峰值（V tri）和固定为参考频率值的频率（fb1） （f ck），供电电位变化。

    Switched capacitance circuit
    30.
    发明公开
    Switched capacitance circuit 审中-公开
    Schaltkreis getakteterKapazitäten

    公开(公告)号：EP1594230A1

    公开(公告)日：2005-11-09

    申请号：EP04425319.3

    申请日：2004-05-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco

    IPC: H03M1/00

    CPC classification number: G11C27/026 ,  G11C27/024 ,  H03H19/004 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/0682 ,  H03M1/468

    Abstract: A switched capacitance circuit including:

    a switched capacitance section, receiving an input signal sampling said signal connected to a common node;
    an operational stage, connected to said common node and providing a current to said common node for charging said capacitors during a sampling time interval of said signal.
    The circuit further includes an auxiliary circuit (ANC) connected to said common node and being activated/deactivated for increasing the current provided to said common node during at least one time interval equal to a fraction of said sampling interval.

    Abstract translation: 一种开关电容电路，包括：开关电容部分，接收对连接到公共节点的所述信号进行采样的输入信号; 操作级，连接到所述公共节点，并在所述信号的采样时间间隔期间向所述公共节点提供电流以对所述电容器充电。 电路还包括连接到所述公共节点并被激活/去激活的辅助电路（ANC），用于在等于所述采样间隔的一部分的至少一个时间间隔期间增加提供给所述公共节点的电流。

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