公开(公告)号：EP2947660B1

公开(公告)日：2017-04-12

申请号：EP15167701.0

申请日：2015-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Pagano, Santi Nunzio Antonino

IPC: G11C7/12 ,  G11C16/24 ,  G11C16/28

CPC classification number: G11C7/062 ,  G11C7/1051 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002

Abstract: A solution relating to a sense structure is proposed. Particularly, the sense structure (200) comprises a plurality of sense amplifiers (205 i ), each sense amplifier comprising at least one measuring terminal (INm) and a reference terminal (INr) for receiving a measuring current (Im) and a reference current (Ir), respectively, output means (225) for providing an output voltage (Vout) according to a comparison between the measuring current and the reference current, and voltage regulating means in cascode configuration (220m,220r) for regulating a voltage at the measuring terminal and at the reference terminal, the regulating means comprising a measuring regulating transistor (220m) and a reference regulating transistor (220r) having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output means and a control terminal coupled with a biasing terminal (Tb), the sense structure further comprising biasing means (230) for providing a biasing voltage (Vb) to the biasing terminal of all the sense amplifiers, and common regulating means (235) for regulating the biasing voltage for all the sense amplifiers, wherein each sense amplifier further comprises local regulating means (240) for regulating the biasing voltage applied to the biasing terminal, and in that the sense structure further comprises switching means (245) selectively controllable for coupling the local regulating means of each sense amplifier with the common regulating means to refresh the local regulating means in a rest condition and for decoupling the local regulating means of each sense amplifier from the common regulating means in an operative condition.

公开(公告)号：EP2506411A1

公开(公告)日：2012-10-03

申请号：EP12162766.5

申请日：2012-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Ucciardello, Carmelo ,  Conte, Antonino ,  Pagano, Santi

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M2003/076 ,  Y10T29/49117

Abstract: A charge pump circuit (10) has a plurality of cascaded charge pump stages (S 1 , ..., S N ), each provided with: a first pump capacitor (C u ) connected to a first internal node (U i ) and receiving a first high voltage phase signal (FHX), and a second pump capacitor (C d ) connected to a second internal node (D i ) and receiving a second high voltage phase signal (FHN), complementary with respect to the first; a first transfer transistor (M pU ) coupled between the first internal node (U i ) and an intermediate node (INT), and a second transfer transistor (M pD ) coupled between the second internal node (D i ) and the intermediate node (INT). The first and second high voltage phase signals have a voltage dynamics (VddH) higher than a maximum voltage (Vdd) sustainable by the first and second transfer transistors. The circuit is further provided with a protection stage (12) set between the first internal node (U i ) and second internal node (D i ) and respectively, the first transfer transistor (M pU ) and second transfer transistor (M pD ), for protecting the same transfer transistors from overvoltages.

Abstract translation: 电荷泵电路（10）具有多个级联电荷泵级（S1，...，SN），每个级联电荷泵级（S1，...，SN）分别设置有：连接到第一内部节点（U i）的第一泵电容器（C u） 第一高电压相位信号（FHX​​）和连接到第二内部节点（D i）的第二泵电容器（C d），并接收第二高电压相位信号（FHN），相对于第一高电压相位信号互补; 耦合在第一内部节点（U i）和中间节点（INT）之间的第一传输晶体管（M pU）以及耦合在第二内部节点（D i）和中间节点（INT）之间的第二传输晶体管 INT）。 第一和第二高电压相位信号具有高于由第一和第二传输晶体管可持续的最大电压（Vdd）的电压动态特性（VddH）。 电路还设置有设置在第一内部节点（U i）和第二内部节点（D i）之间以及分别为第一传输晶体管（M pU）和第二传输晶体管（M pD）的保护级（12） 用于保护相同的转移晶体管免受过电压。

公开(公告)号：EP2320295A1

公开(公告)日：2011-05-11

申请号：EP10189487.1

申请日：2010-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Grasso, Rosario Roberto ,  Giaquinta, Maria

IPC: G05F3/30 ,  H03F3/393

CPC classification number: G05F3/30 ,  H03F3/347 ,  H03F3/45183 ,  H03F2203/45466

Abstract: A bandgap voltage reference circuit ( 100 ) for generating a bandgap voltage reference ( Vbg ). Said circuit comprises a current generator ( 104 ) controlled by a first driving voltage ( Vpgate ) for generating a first current ( Iptat ) depending on the driving voltage, and a first reference circuit element ( 102 ) coupled to the controlled current generator ( 104 ) for receiving the first current and generating a first reference voltage ( Vpluse ) in response to the first current. The circuit further comprises a second reference circuit element ( 106 ) for receiving a second current ( Iptat ) corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage ( Vminuse ) in response to the second current. Said circuit further comprises a third reference circuit element ( 128 ) for receiving a third current ( Iptat ) corresponding to the first current and generating the bandgap reference voltage in response to the third current, and an operational amplifier ( 124 ). The operational amplifier has a first input terminal coupled to the first circuit element for receiving a first reference voltage input ( Vplus ) based on the first reference voltage, a second input terminal coupled to the second reference circuit element for receive a second input voltage ( Vminus ) based on the second reference voltage and an output terminal coupled to the controlled current generator to provide the first driving voltage ( Vpgate ) to the current generator according to the difference between the first input voltage and the second input voltage. The circuit also comprises a control circuit ( 134 ) comprising first capacitive means ( 136 ) and second capacitive means ( 138 ). The first capacitive means have a first terminal coupled to the first reference circuit element to receive the first reference voltage and a second terminal coupled to the first input terminal to provide the first input voltage. The second capacitive means comprise a first terminal coupled to the second reference circuit element for receiving the second reference voltage and a second terminal coupled to the second input terminal to provide the second input voltage. The control circuit also comprises biasing means ( 140 ) to selectively provide a common-mode voltage ( Vcm ) to the second terminals of the first and second capacitive means.

Abstract translation: 一种用于产生带隙电压基准（Vbg）的带隙电压参考电路（100）。 所述电路包括由第一驱动电压（Vpgate）控制的电流发生器（104），用于根据驱动电压产生第一电流（Iptat），以及耦合到受控电流发生器（104）的第一参考电路元件（102） 用于接收第一电流并响应于第一电流产生第一参考电压（Vpluse）。 电路还包括用于接收对应于第一电流的第二电流（Iptat）的第二参考电路元件（106） 所述第二参考电路元件适于响应于第二电流产生第二参考电压（Vminuse）。 所述电路还包括第三参考电路元件（128），用于接收对应于第一电流的第三电流（Iptat）并响应于第三电流产生带隙参考电压，以及运算放大器（124）。 运算放大器具有耦合到第一电路元件的第一输入端，用于基于第一参考电压接收第一参考电压输入（Vplus）;耦合到第二参考电路元件的第二输入端，用于接收第二输入电压（Vminus ）和耦合到受控电流发生器的输出端子，以根据第一输入电压和第二输入电压之间的差异向电流发生器提供第一驱动电压（Vpgate）。 电路还包括包括第一电容装置（136）和第二电容装置（138）的控制电路（134）。 第一电容装置具有耦合到第一参考电路元件以接收第一参考电压的第一端子和耦合到第一输入端子以提供第一输入电压的第二端子。 第二电容装置包括耦合到第二参考电路元件用于接收第二参考电压的第一端子和耦合到第二输入端子以提供第二输入电压的第二端子。 控制电路还包括偏置装置（140），以选择性地向第一和第二电容装置的第二端子提供共模电压（Vcm）。

公开(公告)号：EP1566809B1

公开(公告)日：2006-11-29

申请号：EP04290449.0

申请日：2004-02-19

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics S.A.

Inventor： Demange, Nicolas ,  Conte, Antonino ,  Preciso, Salvatore ,  Signorello, Alfredo

IPC: G11C7/14 ,  G11C7/10

CPC classification number: G11C7/062 ,  G11C7/14 ,  G11C16/28

公开(公告)号：EP1229420B1

公开(公告)日：2006-04-12

申请号：EP01830059.0

申请日：2001-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Concepito, Oreste

IPC: G05F3/30

CPC classification number: G05F3/30

公开(公告)号：EP1492218A1

公开(公告)日：2004-12-29

申请号：EP03425404.5

申请日：2003-06-24

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Castaldo, Enrico

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: A regulator circuit for a charge pump voltage generator comprises a voltage comparator means (400) for performing a voltage comparison between a charge pump output voltage (Vout) and a reference voltage (Vbg), and means (425) responsive to the voltage comparator means for conditioning a charge pump clocking to the result of the voltage comparison. The voltage comparator means includes sampling means (C3,C4,SW3-SW5,SMP) for sampling the charge pump output voltage at a sampling rate. Sampling rate control means (410,415) are provided, responsive to the voltage comparison, for controlling the sampling rate according to the result of the voltage comparison.

Abstract translation: 电路具有用于比较电荷泵输出电压和参考电压的电压比较器（400）。 时钟控制（425）基于比较结果来调节电荷泵时钟。 比较器具有采样单元，用于以采样率对电荷泵输出电压进行采样。 分频器（415）和频率选择状态机（410）基于电压比较结果来控制采样率。 还包括以下独立权利要求：（a）包括电荷泵电压发生器和电荷泵调节器电路的集成电路（b）调节电荷泵电压发生器的输出电压的方法。

公开(公告)号：EP1253499A1

公开(公告)日：2002-10-30

申请号：EP01830275.2

申请日：2001-04-27

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Concepito, Oreste

IPC: G05F3/22

CPC classification number: G05F3/242

Abstract: The present invention relates to a current reference circuit for low supply voltages comprising a current source (I), connected at a side to a supply voltage (Vcc) and to the other side to a series (21) composed by a resistance (R2) and diode (D1), said diode (D1) having the cathode electrode connected to the ground and the anode electrode connected with said resistance (R2), characterized in that to comprise also a transistor (M1) and an operational amplifier (OP), said transistor (M1) having the gate electrode connected to the output of said operational amplifier (OP), said transistor (M1) having the source electrode connected to the ground, said transistor (M1) having the drain electrode connected to the positive electrode of said operational amplifier (OP), with said current source (I) and with said series (21), said operational amplifier (OP) having the negative electrode connected to a band gap reference voltage (V BG ).

Abstract translation: 本发明涉及一种用于低电源电压的电流参考电路，其包括在电源电压（Vcc）一侧连接的电流源（I），另一侧连接到由电阻（R2）组成的串联（21） 和二极管（D1），所述二极管（D1）具有连接到地的阴极和与所述电阻（R2）连接的阳极电极，其特征在于，还包括晶体管（M1）和运算放大器（OP） 所述晶体管（M1）具有连接到所述运算放大器（OP）的输出端的栅电极，所述晶体管（M1）的源电极连接到地，所述晶体管（M1）的漏电极连接到 所述运算放大器（OP）具有所述电流源（I）和所述系列（21），所述运算放大器（OP）具有连接到带隙基准电压（VBG）的负电极。

公开(公告)号：EP1229420A1

公开(公告)日：2002-08-07

申请号：EP01830059.0

申请日：2001-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Concepito, Oreste

IPC: G05F3/30

CPC classification number: G05F3/30

Abstract: Bandgap type reference voltage source using an operational transimpedance amplifier (31). The bandgap stage is formed by a first and a second bandgap branch (2, 3) parallel-connected; the first bandgap branch (2) comprises a first diode (6) and a transistor (5), series-connected and forming a first output node (10); the second bandgap branch (3) comprises a second diode (9) and a second transistor (7) series-connected and forming a second output node (11). The operational amplifier (31) has inputs (31a, 31b) connected to the output nodes (10, 11) of the bandgap stage (18). An amplifier current detecting stage (40) is connected to the outputs (37a, 38a) of the operational amplifier (31) and supplies a current (I RES ) related to the current drawn by the operational amplifier (31). A diode current detecting stage (41) is connected to the output (40c) of the amplifier current detecting stage (40) and to an output (38a) of the operational amplifier (31) and supplies a current (I D ) related to the current (I) flowing in the first diode (6). An output stage (33) transforms this current into a stabilized voltage.

Abstract translation: 带隙型参考电压源，使用运算跨阻放大器（31）。 带隙级由并联的第一和第二带隙分支（2,3）形成; 第一带隙分支（2）包括串联连接并形成第一输出节点（10）的第一二极管（6）和晶体管（5）。 第二带隙分支（3）包括串联连接并形成第二输出节点（11）的第二二极管（9）和第二晶体管（7）。 运算放大器（31）具有连接到带隙级（18）的输出节点（10,11）的输入端（31a，31b）。 放大器电流检测级（40）连接到运算放大器（31）的输出（37a，38a），并提供与运算放大器（31）所绘制的电流相关的电流（IRES）。 二极管电流检测级（41）连接到放大器电流检测级（40）的输出（40c）和运算放大器（31）的输出（38a），并提供与电流相关的电流（ID） （I）在第一二极管（6）中流动。 输出级（33）将该电流转换成稳定的电压。

公开(公告)号：EP2947660A1

公开(公告)日：2015-11-25

申请号：EP15167701.0

申请日：2015-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Micciche', Mario ,  Pagano, Santi Nunzio Antonino

IPC: G11C7/12 ,  G11C16/24 ,  G11C16/28

CPC classification number: G11C7/062 ,  G11C7/1051 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002

Abstract: A solution relating to a sense structure is proposed. Particularly, the sense structure (200) comprises a plurality of sense amplifiers (205 i ), each sense amplifier comprising at least one measuring terminal (INm) and a reference terminal (INr) for receiving a measuring current (Im) and a reference current (Ir), respectively, output means (225) for providing an output voltage (Vout) according to a comparison between the measuring current and the reference current, and voltage regulating means in cascode configuration (220m,220r) for regulating a voltage at the measuring terminal and at the reference terminal, the regulating means comprising a measuring regulating transistor (220m) and a reference regulating transistor (220r) having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output means and a control terminal coupled with a biasing terminal (Tb), the sense structure further comprising biasing means (230) for providing a biasing voltage (Vb) to the biasing terminal of all the sense amplifiers, and common regulating means (235) for regulating the biasing voltage for all the sense amplifiers, wherein each sense amplifier further comprises local regulating means (240) for regulating the biasing voltage applied to the biasing terminal, and in that the sense structure further comprises switching means (245) selectively controllable for coupling the local regulating means of each sense amplifier with the common regulating means to refresh the local regulating means in a rest condition and for decoupling the local regulating means of each sense amplifier from the common regulating means in an operative condition.

Abstract translation: 的溶液与感结构的提议。 特别地，感测结构（200）包括读出放大器（205 i）中，每个读出放大器，其包括至少一个测量终端（INM）和用于接收测量电流（Im）和参考电流的参考端子（INR）的多元 （IR），分别输出装置（225），用于雅丁用于在调节电压的提供关于输出电压（Vout），以测量电流和参考电流，以及电压调节级联配置（220米，220R）的装置之间的比较 测量端子和基准端子，所述调节装置包括一个测量调节晶体管（220米）和参考调节晶体管（220R），其具有耦合与测量端子，并与所述基准端子连接的第一导通端子，分别，第二传导端耦接 与输出装置和耦合的偏置端子（Tb）的控制端子，感测结构，还包括用于提供偏压的偏压装置（230） 用于调节的偏置电压对于所有的读出放大器，worin每个读出放大器进一步荷兰国际集团电压（Vb）中的所有读出放大器的偏置端子，以及共同调节装置（235）包括用于调节所述偏置电压本地调节装置（240） 施加到偏置端子，并且在没有感测结构还包括开关装置（245）选择性地控制用于每个读出放大器的局部调节装置与共同调节耦合装置来刷新本地调节在静止状态装置和用于去耦的 从共用调节每个读出放大器的局部调节装置的装置在运行条件。

公开(公告)号：EP2506411B1

公开(公告)日：2014-12-17

申请号：EP12162766.5

申请日：2012-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Ucciardello, Carmelo ,  Conte, Antonino ,  Pagano, Santi

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M2003/076 ,  Y10T29/49117