公开(公告)号：EP0772244B1

公开(公告)日：2000-03-22

申请号：EP95830468.5

申请日：1995-11-06

Applicant: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno ,  STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio ,  Ferla, Giuseppe ,  Rinaudo, Salvatore

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/66712

Abstract: A MOS technology power device comprises a plurality of elementary functional units, each elementary functional unit comprising a body region (3) of a first conductivity type formed in a semiconductor material layer (2) of a second conductivity type having a first resistivity value. Under each body region (3) a respective lightly doped region (20) of the second conductivity type is provided having a second resistivity value higher than said first resistivity value.

公开(公告)号：EP0506170B1

公开(公告)日：1999-09-08

申请号：EP92200748.9

申请日：1992-03-17

Applicant: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno ,  STMicroelectronics S.r.l.

Inventor： Frisina Ferruccio ,  Ferla, Giuseppe

IPC: H01L27/07 ,  H01L21/22

CPC classification number: H01L27/0761 ,  H01L21/221 ,  Y10S438/904

公开(公告)号：EP0697728B1

公开(公告)日：1999-04-21

申请号：EP94830394.6

申请日：1994-08-02

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Ferla, Giuseppe ,  Frisina, Ferruccio

IPC: H01L23/495 ,  H01L29/78 ,  H01L29/72

CPC classification number: H01L24/06 ,  H01L23/4824 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L29/41741 ,  H01L29/7802 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01039 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/45015 ,  H01L2924/207

公开(公告)号：EP1643558B1

公开(公告)日：2012-05-02

申请号：EP04425733.5

申请日：2004-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferrucio ,  Ferla, Giuseppe ,  Magri', Angelo

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/732 ,  H01L29/861 ,  H01L29/417 ,  H01L29/06 ,  H01L21/336 ,  H01L21/331 ,  H01L21/329 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

公开(公告)号：EP0689239B1

公开(公告)日：2007-03-07

申请号：EP94830316.9

申请日：1994-06-23

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Ferla, Giuseppe ,  Frisina, Ferruccio

IPC: H01L21/336

CPC classification number: H01L29/66712 ,  H01L21/26586 ,  H01L29/1095

公开(公告)号：EP1659636A1

公开(公告)日：2006-05-24

申请号：EP05025285.7

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Ferruccio, Frisina ,  Ferla, Giuseppe ,  Magri', Angelo ,  Grimaldi, Antonio Giuseppe ,  Bazzano, Gaetano

IPC: H01L29/78 ,  H01L29/49

CPC classification number: H01L29/7802 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4983

Abstract: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors (2) and a gate structure (12) comprising a plurality of conductive strips (8) realised with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks (11) connected to a gate pad (30) and at least a connection layer (20) arranged in series to at least one of said conductive strip (8). Such gate structure (12) comprising at least a plurality of independent islands (10) formed on the upper surface (9) of the conductive strips (8) and suitably formed on the connection layers (20). Said islands (10) being realised with at least one second conductive material such as silicide.

Abstract translation: 包括多个基本功率MOS晶体管（2）和栅极结构（12）的功率电子MOS器件包括由诸如多晶硅的第一导电材料实现的多个导电条（8），多个栅极指或者 连接到栅极焊盘（30）的金属轨道（11）和至少与所述导电条（8）中的至少一个串联布置的连接层（20）。 这种栅极结构（12）包括形成在导电条（8）的上表面（9）上并适当地形成在连接层（20）上的至少多个独立的岛（10）。 所述岛（10）用至少一种第二导电材料（例如硅化物）实现。

公开(公告)号：EP0772242B1

公开(公告)日：2006-04-05

申请号：EP95830454.5

申请日：1995-10-30

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Frisina, Ferruccio ,  Magri', Angelo ,  Ferla, Giuseppe

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66333

Abstract: A MOS technology power device comprises: a semiconductor material layer (2) of a first conductivity type; a conductive insulated gate layer (7,8,9) covering the semiconductor material layer (2); a plurality of elementary functional units, each elementary functional unit comprising a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of an elongated body stripe, each elementary functional unit further comprising an elongated window (12) in the insulated gate layer (7,8,9) extending above the elongated body stripe (3). Each body stripe (3) includes at least one source portion (60;61;62) doped with dopants of the first conductivity type, intercalated with a body portion (40;41;3') of the body stripe (3) wherein no dopant of the first conductivity type are provided. The conductive insulated gate layer (7,8,9) comprises a first insulating material layer (7) placed above the semiconductor material layer (2), a conductive material layer (8) placed above the first insulating material layer (7), and a second insulating material layer (9) placed above the conductive material layer (8). Insulating material sidewall spacers (13) are provided to seal edges of the elongated window (12) in the insulated gate layer (7,8,9).

公开(公告)号：EP1450411A1

公开(公告)日：2004-08-25

申请号：EP03425099.3

申请日：2003-02-21

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio ,  Ferla, Giuseppe ,  Magri', Angelo ,  Salinas, Dario

IPC: H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66712

Abstract: A MOS power device having: a body (10); gate regions (34) on top of the body (10) and delimiting therebetween a window (40); a body region (35), extending in the body underneath the window; a source region (36), extending inside the body region (35) throughout the width of the window; body contact regions (43), extending through the source region up to the body region; source contact regions (46), extending inside the source region, at the sides of the body contact regions; a dielectric region (41) on top of the source region; openings (42, 45) traversing the dielectric region on top of the body and source contact regions (43, 46); and a metal region (50) extending above the dielectric region (41) and through the first and second openings (42, 45).

Abstract translation: 一种MOS功率器件，具有：主体（10）; 门区域（34）在主体（10）的顶部上并在其间界定窗口（40）; 身体区域（35），其在所述窗户下方的身体中延伸; 源区域（36），其在所述窗体的整个宽度内在所述体区域（35）内延伸; 身体接触区域（43），延伸穿过源区域直到身体区域; 源极接触区域（46），其在源极区域内延伸，位于身体接触区域的侧面; 在所述源极区域的顶部上的电介质区域（41） 穿过主体顶部的电介质区域和源极接触区域（43,46）的开口（42,45）; 以及在所述电介质区域（41）上方延伸并且穿过所述第一和第二开口（42,45）的金属区域（50）。

公开(公告)号：EP0772241B1

公开(公告)日：2004-06-09

申请号：EP95830453.7

申请日：1995-10-30

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Magri', Angelo ,  Frisina, Ferruccio ,  Ferla, Giuseppe

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66712

Abstract: A MOS technology power device comprises a plurality of elementary functional units which contribute for respective fractions to an overall current of the power device and which are formed in a semiconductor material layer (2) of a first conductivity type. Each elementary functional unit comprises a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of a body stripe (3) elongated in a longitudinal direction on a surface of the semiconductor material layer (2). Each body stripe (3) includes at least one source portion (60) doped with dopants of the first conductivity type which is intercalated with a body portion (40) of the body stripe (3) wherein no dopants of the first conductivity type are provided.

公开(公告)号：EP0749158B1

公开(公告)日：2001-10-31

申请号：EP95830249.9

申请日：1995-06-16

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  STMicroelectronics S.r.l.

Inventor： Santangelo, Antonello ,  Ferla, Giuseppe

IPC: H01L23/00 ,  H01L29/739 ,  H01L29/78 ,  H01L29/43 ,  H01L21/331

CPC classification number: H01L29/7802 ,  H01L29/49 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic semiconductor device (20) with a control electrode (19) consisting of self-aligned polycrystalline silicon (4) and silicide (12), of the type in which said control electrode (19) is formed above a portion (1) of semiconductor material which accommodates active areas (9) of the device (20) laterally with respect to the electrode, has the active areas (9) at least partially protected by an oxide layer (10) while the silicide layer (12) is obtained by means of direct reaction between a metal film deposited on the polycrystalline silicon (4) and on the oxide layer (10).