公开(公告)号：EP1460542A1

公开(公告)日：2004-09-22

申请号：EP03425171.0

申请日：2003-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1048

Abstract: The present invention relates to an integrated memory system (1) comprising at least a non volatile memory (2) and an automatic storage error corrector, and wherein the memory (2) is connected to a controller (3) by means of an interface bus (4). Advantageously, the system comprises in the memory (2) circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal (IRQ) to ask a correction being external to the memory (2).

Abstract translation: 本发明涉及到集成存储系统（1），包括至少一个非易失性存储器（2）和自动存储误差校正器，和worin存储器（2）通过接口总线连接到控制器（3） （4）。 有利地，该系统包括：在存储器（2）的电路装置，在功能上独立的，每个负责一个预定的存储误差的修正; 产生一个信号（IRQ）问的校正是外部存储器。所述装置的至少一个（2）。

公开(公告)号：EP1635261A1

公开(公告)日：2006-03-15

申请号：EP04425678.2

申请日：2004-09-10

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Bovino, Angelo ,  Altieri, Vincenzo

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: A memory (104) has one bus (112) for data, addresses, and commands. A data register (114) is coupled to the bus (112) to store the data written to and read from the memory (104), a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code (ECC) circuit for calculating an ECC. The memory (104) is configured (168, 200, 206, 237) to be responsive to external commands for controlling the operation of the ECC circuit (140) for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

Abstract translation: 存储器（104）具有用于数据，地址和命令的一个总线（112）。 数据寄存器（114）耦合到总线（112）以存储写入存储器（104）和从存储器（104）读取的数据，命令寄存器耦合到总线以接收存储器命令，并且地址寄存器耦合到 总线来解决内存。 存储器还包括用于计算ECC的纠错码（ECC）电路。 存储器（104）被配置为响应于用于控制ECC电路（140）的操作的外部命令，用于读取或写入与控制读取或写入的外部命令分离的ECC 的内存数据。 存储器还可以包括状态寄存器，其存储关于ECC的通过或失败的信息。

公开(公告)号：EP1435625A1

公开(公告)日：2004-07-07

申请号：EP02425808.9

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Khouri, Osama ,  Ravasio, Roberto ,  Micheloni, Rino ,  Campardo, Giovanni

IPC: G11C29/00

CPC classification number: G11C29/76

Abstract: A non volatile memory of the type comprising a predetermined number of sectors capable of ensuring the operation of the same even with a lower number of defective sectors than a predetermined limit.

Abstract translation: 这种类型的非易失性存储器包括能够确保即使具有比预定极限更少数量的缺陷扇区的扇区的预定数量的扇区。

公开(公告)号：EP1729306A1

公开(公告)日：2006-12-06

申请号：EP05104742.1

申请日：2005-06-01

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Motta, Ilaria

IPC: G11C16/34

CPC classification number: G11C16/3404 ,  G11C16/3409

Abstract: A flash memory device with NAND architecture (100) is proposed. The memory device includes a matrix of memory cells (110) each one having a programmable threshold voltage, wherein the matrix includes at least one sector individually erasable (115) and it is arranged in a plurality of rows and columns with the cells of each row connected to the corresponding word line (WL) and the cells of each column arranged in a plurality of strings (125) of cells connected in series, the strings of each column being connected to a corresponding bit line (BL), wherein the memory device further includes means (320) for erasing the cells of a selected sector, and means (330) for restoring the threshold voltage of the erased cells, wherein the means for restoring acts in succession on each of a plurality of blocks of the sector, for each one of a set of selected bit lines the block including a group of cells connected to a set of selected word lines, the means for restoring including means (446a, 446b) for reading each group with respect to a limit value exceeding a reading reference value, means (451a, 451b) for programming only each group wherein the threshold voltage of at least one group does not reach said limit value, and means (449a, 449b) for stopping the restoring in response to the reaching of the limit value by at least one sub-set of the groups.

Abstract translation: 提出了具有NAND架构（100）的闪存器件。 存储器件包括每个具有可编程阈值电压的存储器单元（110）的矩阵，其中该矩阵包括至少一个可单独地擦除的扇区（115），并且它被布置成多个行和列，每行的单元格 连接到相应的字线（WL）和排列成串联连接的多个单元串（125）的每列的单元，每列的串连接到对应的位线（BL），其中存储器件 还包括用于擦除所选扇区的单元的装置（320），以及用于恢复已擦除单元的阈值电压的装置（330），其中用于恢复的装置依次在该扇区的多个块中的每个块上作用， 一组选定位线中的每一个，包括连接到一组所选字线的一组单元的单元，所述恢复装置包括用于相对于超过一个限制值的每个组读取每个组的装置（446a，446b） 读取参考值，用于仅编程至少一个组的阈值电压未达到所述极限值的每个组的装置（451a，451b）以及用于响应于达到极限而停止恢复的装置（449a，449b） 至少一个组的子集的值。

公开(公告)号：EP1612950A1

公开(公告)日：2006-01-04

申请号：EP04425486.0

申请日：2004-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/1555 ,  H03M13/152 ,  H03M13/6561

Abstract: The invention relates to a method and system for correcting errors in multilevel memories, both of the NAND and of the NOR type. The method provides the use of a BCH correction code made parallel by means of a coding and decoding architecture allowing the latency limits of prior art sequential solutions to be overcome. Two possible solutions are shown.
The parallelism being used for blocks C, 1 and 3 can be chosen in order to optimise the system performances in terms of latency and device area.

Abstract translation: 本发明涉及一种方法和系统，用于多级存储器校正错误，这两种类型的NAND和NOR。 该方法提供使用的BCH纠错码由编码和解码架构，允许现有技术解决方案的顺序的延迟限制的方式作出平行于被克服。 两种可能的解决方案中。 正在使用的并行用于块C，1和3可以以优化系统性能的延迟和设备面积方面进行选择。

公开(公告)号：EP1460765A1

公开(公告)日：2004-09-22

申请号：EP03425172.8

申请日：2003-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Lunelli, Massimiliano ,  Micheloni, Rino ,  Ravasio, Roberto ,  Marelli, Alessia

IPC: H03M13/13 ,  H03M13/15 ,  H03M13/19

CPC classification number: H03M13/1575 ,  H03M13/13 ,  H03M13/15 ,  H03M13/19

Abstract: A method for making error corrections on digital information coded as symbol sequences ( x ), for example digital information stored in electronic memory systems or transmitted from and to these systems is described, providing the transmission of sequences ( x ) incorporating a portion of error corrector code allowing the sequence ( x ) which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received.
Advantageously according to the invention, the error code incorporated in the original sequence ( x ) belongs to a non Boolean group.

Abstract translation: 描述了用于对编码为符号序列（x）的数字信息进行纠错的方法，例如存储在电子存储器系统中或从这些系统发送的数字信息，或从这些系统发送和传送到这些系统的方法，提供包含错误校正器的一部分的序列（x） 允许更可能是通过使用奇偶校验矩阵计算误差校正子传送的序列（x）的序列（x），以便在接收时恢复。 有利地，根据本发明，并入原始序列（x）中的错误代码属于非布尔组。

公开(公告)号：EP1830269B1

公开(公告)日：2009-05-13

申请号：EP06425141.6

申请日：2006-03-02

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Intini, Valeria ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18

公开(公告)号：EP1830269A1

公开(公告)日：2007-09-05

申请号：EP06425141.6

申请日：2006-03-02

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Intini, Valeria ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A 0 , A 1 , ..., A LS-1 ) to generate a first recovered string (S 1 ), and performing a first decoding attempt using the first recovered string (S 1 ). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S 2 -S N ) is generated. On the basis of a comparison between the first recovered string (S 1 ) and the second recovered string (S 2 -S N ), a modified string (S M ) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (S M ).

Abstract translation: 用于与错误校正编码的存储器装置的读出方法设想如下步骤：执行的存储器位置处的多个第一读取（A 0，A 1，...，A LS-1），以产生一个第一回收串 （S 1），并执行使用第一回收串（S 1）的第一解码尝试。 当第一解码尝试失败，存储器位置被读取的至少一个第二时间，并且至少一个第二回收串（S 2 -S N）被产生。 在第一回收串（S 1）和所述第二回收串（S 2 -S N）之间的比较的基础上，产生一个修改后的字符串（SM），其中擦除（X）的位置，和至少一个第二 解码尝试是使用修改后的字符串（SM）。

公开(公告)号：EP1420415A3

公开(公告)日：2007-02-28

申请号：EP03104130.4

申请日：2003-11-10

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A circuit (115,145,150) for programming a non-volatile memory device (100) having a plurality of memory cells (105) is proposed. The circuit includes a plurality of driving elements (115) each one for applying a program pulse to a selected memory cell to be programmed, the driving elements being suitable to be supplied by a power supply unit (120,125), and control means (145,150) for controlling the driving elements; the control means includes means (150,205) for determining a residual capacity of the power supply unit, and selecting means (145) for selectively enabling the driving elements according to the residual capacity.

公开(公告)号：EP1612949A1

公开(公告)日：2006-01-04

申请号：EP04425485.2

申请日：2004-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/152 ,  H03M13/1575 ,  H03M13/3707 ,  H03M13/6502

Abstract: The invention relates to a method and system for correcting errors in multilevel memories using binary BCH codes. The number of errors is estimated by analyzing the syndrome components (5). If the number of estimated errors is one, then simple decoding for a Hamming code is performed. Otherwise, conventional decoding of the BCH code is carried out (2,3). This avoids the computation of the error locator polynomial and its roots in the presence of only one error and, thus, reduces the average decoding complexity.

Abstract translation: 本发明涉及一种使用二进制BCH码对多层存储器中的错误进行校正的方法和系统。 通过分析综合征成分估计误差数（5）。 如果估计误差的数量为1，则执行汉明码的简单解码。 否则，执行BCH码的常规解码（2,3）。 这避免了在仅存在一个错误的情况下计算错误定位器多项式及其根，并因此降低平均解码复杂度。