公开(公告)号：JPS62130595A

公开(公告)日：1987-06-12

申请号：JP26937185

申请日：1985-12-02

Applicant: TOSHIBA CORP

Inventor： SAITO MASAYUKI ,  OHIRA HIROSHI ,  YOSHIDA KENICHI

IPC: H01L23/28 ,  H05K3/12 ,  H05K3/28

公开(公告)号：JPS61208895A

公开(公告)日：1986-09-17

申请号：JP4930485

申请日：1985-03-14

Applicant: TOSHIBA CORP

Inventor： SAITO MASAYUKI ,  OHIRA HIROSHI

IPC: H05K3/44

公开(公告)号：JPS6129112A

公开(公告)日：1986-02-10

申请号：JP14929684

申请日：1984-07-20

Applicant: Toshiba Corp

Inventor： HARADA MITSUO ,  YAMASHITA YOHACHI ,  TAKAHASHI TAKASHI ,  SAITO MASAYUKI ,  OHIRA HIROSHI

IPC: H01G4/12 ,  H01G4/06 ,  H01G4/33

公开(公告)号：JP2000268701A

公开(公告)日：2000-09-29

申请号：JP6928599

申请日：1999-03-15

Applicant: TOSHIBA CORP

Inventor： YAMAMOTO MASAHIKO ,  FUKUDA YUMI ,  MORI MIKI ,  KOBAYASHI HITOSHI ,  HARA YUJIRO ,  ITO TAKESHI ,  SAITO MASAYUKI ,  HIRAOKA TOSHIRO ,  ASAKAWA KOUJI

IPC: H01J1/304 ,  H01J1/30 ,  H01J1/62 ,  H01J9/02 ,  H01J9/18 ,  H01J29/04 ,  H01J31/12 ,  H01J63/04

Abstract: PROBLEM TO BE SOLVED: To provide a uniform display element in a large area with a long service life and high fineness capable of easily suppressing unevenness of the amount of emitted electrons and being driven at low voltage when many elements are formed with an electron emitting element using a fine particles emitter in a large area. SOLUTION: An electron emitting element has a substrate 1, a cathode wiring layer 2 formed on the substrate 1, a gate wiring layer 6, and an insulating layer 5 electrically insulating the cathode wiring layer 2 from the gate wiring layer 6, and is formed with a resistance layer 3 and an emitter layer 4 in a through hole piercing the gate wiring layer 6 and the insulating layer 5. The resistance layer 3 is formed by dispersing conductive fine particles 3b in a base material consisting of insulating fine particles 3a. The emitter layer 4 is formed of a fine particle material. The insulating layer on the first substrate formed with a cathode electrode line, the emitter layer, the insulating layer, and a gate electrode line in its order consists of a silicon dioxide film contains fluorine.

公开(公告)号：JPH10135479A

公开(公告)日：1998-05-22

申请号：JP19138197

申请日：1997-07-16

Applicant: TOSHIBA CORP

Inventor： FUKUDA YUMI ,  MORI MIKI ,  IIDA ATSUKO ,  SAITO MASAYUKI ,  ATSUTA MASAKI ,  OGAWA YOSHIFUMI ,  KIZAKI YUKIO ,  IKEDA MITSUSHI ,  ASHIDA SUMIO ,  KOBAYASHI HITOSHI ,  ONOZUKA YUTAKA ,  HIGUCHI KAZUTO

IPC: G01T1/24 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/40 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide an image display device that is laminated structure but yet is small in non-display area and high in mechanical strength and has a reliable large screen. SOLUTION: The transistor array is formed by joining a first translucent substrate 200a with a plurality of transistors 203 and transparent conductive films 205 formed thereon, with a second translucent substrate 200b with a plurality of transistors 203 and transparent conductive films 205 formed thereon, on their sides. The transparent conductive films are placed between the joint 207 between the first and second translucent substrates 200a, 200b, and the transistors nearest to the joint 207.

公开(公告)号：JPH10104651A

公开(公告)日：1998-04-24

申请号：JP25573996

申请日：1996-09-27

Applicant: TOSHIBA CORP

Inventor： MORI MIKI ,  SAITO MASAYUKI ,  MATSUMOTO KAZUHIRO ,  MURAKAMI TAIJUN

IPC: G02F1/1345

Abstract: PROBLEM TO BE SOLVED: To improve driving characteristics of a driving circuit, to improve the reliability of the display device in spite of large capacity and high definition, and to obtain an image of high quality by making low the resistance of wires patterned on the electrode substrate of a driving circuit mounted directly on an electrode substrate. SOLUTION: A signal line driving IC 14 mounted on the electrode formation surface 10a of the electrode substrate is supplied with a signal from a reverse- surface wiring pattern 20 formed on the reverse surface 10b of the electrode substrate 10 through a 2nd through hole 22 to make small the resistance of the reverse-surface wiring pattern 10 and then a wiring pattern 18 formed on the electrode formation surface 10a without increasing a frame area B of the electrode substrate 20, thereby improving driving characteristics of the signal line driving IC and a gate line driving IC.

公开(公告)号：JPH1092981A

公开(公告)日：1998-04-10

申请号：JP24505196

申请日：1996-09-17

Applicant: TOSHIBA CORP

Inventor： HONMA SOICHI ,  IZEKI YUJI ,  ONOMURA JIYUNKO ,  YAMADA HIROSHI ,  SAITO MASAYUKI

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/552 ,  H01L31/02

Abstract: PROBLEM TO BE SOLVED: To produce a conductive mold package for semiconductor device through simple process requiring a simple shield at low cost while preventing oscillation by filling the gap between a semiconductor chip and a substrate with a nonconductive resin layer and coating the semiconductor chip, on the side and the rear thereof, with a conductive resin layer. SOLUTION: A semiconductor chip 11 is flip chip mounted on an alumina board 13 on which wiring is formed. The gap between the HEMT chip 11 and the alumina board 13 is filled with a nonconductive resin 14, i.e., epoxy resin. Subsequently, the HEMT chip 11 is then coated, on the circumference thereof, with a conductive resin 15. It may be coated by potting or using a die 16. An epoxy based thermosetting resin mixed with 85-95wt.% of acicular silver powder having diameter of 20μm is employed as the conductive resin 15. According to the method, the process is simplified and the yield is increased while reducing the cost. Furthermore, problem of resonance can be eliminated by increasing the resonance frequency.

公开(公告)号：JPH1065057A

公开(公告)日：1998-03-06

申请号：JP21340996

申请日：1996-08-13

Applicant: TOSHIBA CORP

Inventor： HIGUCHI KAZUTO ,  KONNO YOSHIO ,  KURIYAMA YASUHIKO ,  ONO NAOKO ,  SAITO MASAYUKI

IPC: H01L23/12

Abstract: PROBLEM TO BE SOLVED: To mount a semiconductor chip with its face up and reduce the mounting area by using a semiconductor chip having bump electrodes formed on input/output terminals arranged at the marginal area of the chip and electrically connecting the bump electrode side faces to the wiring electrode surface on a board with solder bridges. SOLUTION: Input/output terminals 9 are formed at the marginal area of a base semiconductor chip 2 and bump electrodes 4 formed on the terminals 9. A semiconductor chip 3 mounted on the chip 2 is mounted on a mounting board 1 with a hybrid IC molded with a resin mold 13 and bump electrodes 4 electrically connected to wiring electrodes 11 near the electrodes 4 through bridges 5. The side faces of the electrodes 4 are flush with the side face of the base board 2 and solder bumps formed at the side faces are well connected. Thus it is possible to place the wiring electrodes 11 near round the chip 2 on the board 1 and reduce the mounting area.

公开(公告)号：JPH09172107A

公开(公告)日：1997-06-30

申请号：JP24052796

申请日：1996-09-11

Applicant: TOSHIBA CORP

Inventor： MIYAGI TAKESHI ,  IZEKI YUJI ,  SHIZUKI YASUSHI ,  YOSHIHARA KUNIO ,  SAITO MASAYUKI ,  HIGUCHI KAZUTO ,  HANAWA TAKESHI ,  TAKAGI EIJI

IPC: H01L23/12 ,  H05K1/02 ,  H05K3/10

Abstract: PROBLEM TO BE SOLVED: To avoid the concentration of electric currents by protruding the upper end sections of signal lines laid in wiring forming grooves which are composed of recessed sections having cross sections representing continuous curved surfaces and formed on the surface of a dielectric layer formed on a substrate from the surface of the dielectric layer. SOLUTION: A ground layer 3 and a dielectric layer 4 are successively formed on a substrate 2. Signal lines 5 are buried in recessed sections which are formed on the surface of the dielectric layer 4 and have cross sections representing continuous curved surfaces at a depth of H2 and the end faces of the lines 5 are protruded from the surface of the dielectric layer to a height of H1 . That is the distances from the protruded front ends of the lines 5 to the bottoms of the recessed sections are represented by H(=H1 +H2 ) and the value of the H corresponds to the thickness of the signal lines 5. Since the signal lines 5 are brought into contact with the dielectric layer 4 on the curved surfaces only and no corner section exists in the contacting plane between the dielectric layer 4 and signal lines 5, the concentration of electric currents can be avoided.

公开(公告)号：JPH09153520A

公开(公告)日：1997-06-10

申请号：JP31330595

申请日：1995-11-30

Applicant: TOSHIBA CORP

Inventor： YAMADA HIROSHI ,  TOGASAKI TAKASHI ,  SAITO MASAYUKI

IPC: H01L21/60

Abstract: PROBLEM TO BE SOLVED: To improve the reliability of a flip-chip mounted semiconductor by improving the method of inspecting a semiconductor chip. SOLUTION: Through holes are formed on a thermosetting resin sheet 6 on a wiring pattern 7 to connect between a semiconductor chip 1 formed with bump electrodes 3 and the thermosetting resin sheet 6 formed with the wiring pattern 7 that is the same in the pattern of circuit wiring. Through the through holes, the bump electrodes 3 and the wiring pattern 7 are connected, using the wiring pattern 7 as the electrodes for inspection, the semiconductor chip 1 is inspected and the connecting electrodes 15 of a circuit wiring board 14 and the bump electrodes 3 are connected electrically and mechanically.