公开(公告)号：US20230044537A1

公开(公告)日：2023-02-09

申请号：US17790369

申请日：2020-12-30

Applicant: TSINGHUA UNIVERSITY

Inventor： Liyang PAN ,  Jingyao SUN ,  Huaqiang WU

IPC: G11C13/00

Abstract: A resistive random access memory array and an operation method therefor, and a resistive random access memory circuit. The resistive random access memory array includes multiple memory cells, multiple bit lines, multiple word lines, multiple block selection circuits, and multiple initialization circuits. Each memory cell includes a resistive random access memory device and a switching device. The multiple memory cells are arranged into multiple memory cell rows and multiple memory cell columns in a first direction and a second direction, and the multiple bit lines and the multiple memory cell columns are connected in one-to-one correspondence. Each block selection circuit is configured to write a read/write operation voltage into a correspondingly connected bit line in response to a block selection voltage. Each initialization circuit is configured to write an initialization operation voltage to a correspondingly connected bit line in response to an initialization control voltage.

公开(公告)号：US20230004357A1

公开(公告)日：2023-01-05

申请号：US17779834

申请日：2020-11-13

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Bohan LIN ,  Bin GAO ,  Jianshi TANG ,  He QIAN

IPC: G06F7/58

Abstract: A method for generating a random number and a random number generator are provided. The method for generating a random number includes: performing n writing operations on at least one analog resistive random access memory, where each of the n writing operations includes applying at least one writing operation pulse to change a conductance value of an operated analog resistive access memory; and generating the random number based on n writing operation pulse numbers respectively corresponding to the n writing operations, where n is a positive integer. The method for generating a random number generates random numbers based on the analog characteristics of the analog resistive random access memory, the generated random number does not need back-end correction, and have both high speed and high reliability.

公开(公告)号：US20220335278A1

公开(公告)日：2022-10-20

申请号：US17049348

申请日：2020-01-10

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Peng YAO ,  Bin GAO ,  He QIAN

IPC: G06N3/063 ,  G06F9/345 ,  G06F9/38 ,  G06F9/30

Abstract: Disclosed are a parallel acceleration method for a memristor-based neural network, a parallel acceleration processor based on a memristor-based neural network and a parallel acceleration device based on a memristor-based neural network. The neural network includes a plurality of functional layers sequentially provided, wherein the plurality of functional layers include a first functional layer and a second functional layer following the first functional layer, the first functional layer includes a plurality of first memristor arrays in parallel, and the plurality of first memristor arrays are configured to execute an operation of the first functional layer in parallel and to output a result of the operation to the second functional layer. The parallel acceleration method includes: executing the operation of the first functional layer in parallel via the plurality of first memristor arrays and outputting the result of the operation to the second functional layer.

公开(公告)号：US20220207338A1

公开(公告)日：2022-06-30

申请号：US17560801

申请日：2021-12-23

Applicant: TSINGHUA UNIVERSITY

Inventor： Xinyi LI ,  Huaqiang WU ,  He QIAN ,  Dong WU

IPC: G06N3/063 ,  G06N3/04

Abstract: A neuron simulation circuit and a neural network apparatus. The neuron simulation circuit includes an operational amplifier, a first resistive device and a second resistive device. The operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The first resistive device is connected between the first input terminal or the second input terminal of the operational amplifier and the output terminal of the operational amplifier. The second resistive device is connected between the output terminal of the operational amplifier and an output terminal of the neuron simulation circuit. The second resistive device includes a threshold switching memristor, and a first terminal of the threshold switching memristor is electrically connected with the output terminal of the neuron simulation circuit. At least one of the first resistive device and the second resistive device includes a dynamic memristor.

公开(公告)号：US20220093855A1

公开(公告)日：2022-03-24

申请号：US17477119

申请日：2021-09-16

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  He QIAN ,  Xinyi LI

IPC: H01L45/00 ,  H01L27/24

Abstract: A memristor and a preparation method thereof are provided. The memristor includes at least one memristive unit, each of the at least one memristive unit includes a transistor and at least one memristive component, the transistor includes a source electrode and a drain electrode; and each of the at least one memristive component includes a first electrode, a resistive layer, a second electrode, and a passivation layer, the first electrode is electrically connected with the source electrode or the drain electrode; the resistive layer is provided between the first electrode and the second electrode; and the passivation layer at least covers a sidewall of the resistive layer.

公开(公告)号：US20160118586A1

公开(公告)日：2016-04-28

申请号：US14894502

申请日：2014-05-28

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Minghao WU ,  Yue BAI ,  He QIAN

IPC: H01L45/00

CPC classification number: H01L45/1633 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: A method for forming a stacked structure includes steps of: providing a first layer; oxidizing at least a part of the first layer to form a first oxide layer on the first layer; forming a second layer on the first oxide layer; and forming a second oxide layer between the first oxide layer and the second layer by rapid thermal annealing.

Abstract translation: 一种形成层叠结构的方法包括以下步骤：提供第一层; 氧化所述第一层的至少一部分以在所述第一层上形成第一氧化物层; 在所述第一氧化物层上形成第二层; 以及通过快速热退火在所述第一氧化物层和所述第二层之间形成第二氧化物层。

公开(公告)号：US20160108521A1

公开(公告)日：2016-04-21

申请号：US14740359

申请日：2015-06-16

Applicant: Tsinghua University

Inventor： Huaqiang WU ,  Shuoguo YUAN ,  Han LI ,  He QIAN

IPC: C23C16/455 ,  C23C16/56 ,  C23C16/22 ,  H01J1/304

CPC classification number: H01J1/304 ,  C23C16/305 ,  C23C16/4488 ,  C23C16/45523 ,  H01J9/025 ,  H01J2201/30449

Abstract: The present disclosure relates to a method for preparing a molybdenum disulfide film used in a field emission device, including: providing a sulfur vapor; blowing the sulfur vapor into a reaction chamber having a substrate and MoO3 powder to generate a gaseous MoOx; feeding the sulfur vapor into the reaction chamber sequentially, heating the reaction chamber to a predetermined reaction temperature and maintaining for a predetermined reaction time, and then cooling the reaction chamber to a room temperature and maintaining for a second reaction time to form a molybdenum disulfide film on the surface of the substrate, in which the molybdenum disulfide film grows horizontally and then grows vertically. The method according to the present disclosure is simple and easy, and the field emission property of the MoS2 film obtained is good.

Abstract translation: 本公开涉及一种制备用于场致发射装置的二硫化钼膜的方法，包括：提供硫蒸汽; 将硫蒸气吹入具有基底和MoO 3粉末的反应室中以产生气态MoO x; 将硫蒸气依次进料到反应室中，将反应室加热至预定的反应温度并保持预定的反应时间，然后将反应室冷却至室温并保持第二反应时间以形成二硫化钼膜 在其中二硫化钼膜水平生长然后垂直生长的基底表面上。 根据本公开的方法简单易行，并且所获得的MoS2膜的场发射性能良好。