公开(公告)号：US09368442B1

公开(公告)日：2016-06-14

申请号：US14583755

申请日：2014-12-28

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  Dyi-Chung Hu ,  Yu-Hua Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/3105

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing an interposer includes the following steps. Conductive beads is filled in a blind via of a substrate and a solder layer of each conductive bead is melted so as to form a solder post in the blind via. A metal ball of each conductive bead is inlaid in the corresponding solder post such that the solder post and the metal balls inlaid therein construct a conductive though via. Two surfaces of the substrate are planarized such that two ends of the conductive through via are exposed to the two surfaces of the substrate respectively and are flush with the two surfaces of the substrate respectively. A redistribution layer is manufactured at each surface of the substrate such that the two ends of each conductive through via connect the redistribution layers respectively. Besides, an interposer and a chip package structure applied the interposer are also provided.

Abstract translation: 一种用于制造插入件的方法包括以下步骤。 导电珠填充在基板的盲孔中，并且每个导电珠的焊料层熔化，以在盲孔中形成焊料柱。 每个导电珠的金属球镶嵌在相应的焊料柱中，使得焊接柱和镶嵌在其中的金属球构成导电的通孔。 基板的两个表面被平坦化，使得导电通孔的两个端部分别暴露于基板的两个表面，并分别与基板的两个表面齐平。 在衬底的每个表面处制造再分布层，使得每个导电通孔的两端分别连接重新分布层。 此外，还提供了应用了插入器的插入器和芯片封装结构。

公开(公告)号：US11854961B2

公开(公告)日：2023-12-26

申请号：US17095744

申请日：2020-11-12

Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Tao-Chih Chang ,  Yu-Min Lin ,  Sheng-Tsai Wu

IPC: H01L29/00 ,  H01L23/522 ,  H01L23/498 ,  H01L25/04 ,  H01L21/48

CPC classification number: H01L23/5226 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/04 ,  H01L2924/0002

Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

公开(公告)号：US11445617B2

公开(公告)日：2022-09-13

申请号：US16379816

申请日：2019-04-10

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Cheng-Ta Ko ,  John Hon-Shing Lau ,  Yu-Hua Chen ,  Tzyy-Jang Tseng

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H05K1/14 ,  H01L23/538

Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.

公开(公告)号：US11366381B2

公开(公告)日：2022-06-21

申请号：US16395244

申请日：2019-04-26

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Shih-Lian Cheng ,  Yu-Hua Chen ,  Cheng-Ta Ko ,  Jui-Jung Chien ,  Wei-Tse Ho

IPC: B32B37/00 ,  G03F1/50 ,  H05K3/06 ,  H05K3/24 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12 ,  H05K3/18 ,  H05K3/42 ,  G03F7/20 ,  G01K7/24 ,  G01K15/00

Abstract: A mask structure and a manufacturing method of the mask structure are provided. The mask structure includes a transparent substrate, a patterned metal layer, and a plurality of microlens structures. The patterned metal layer is disposed on the transparent substrate and exposing a portion of the transparent substrate. The microlens structures are disposed on the transparent substrate exposed by a portion of the patterned metal layer and being in contact with the portion of the patterned metal layer.

公开(公告)号：US11251350B2

公开(公告)日：2022-02-15

申请号：US16281108

申请日：2019-02-21

Applicant: Unimicron Technology Corp.

Inventor： Yi-Cheng Lin ,  Yu-Hua Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Cheng-Hui Wu

IPC: H01L33/62 ,  H01L33/52 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31

Abstract: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.

公开(公告)号：US20210398894A1

公开(公告)日：2021-12-23

申请号：US17402635

申请日：2021-08-16

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Yu-Hua Chen

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

Abstract: A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.

公开(公告)号：US10950687B2

公开(公告)日：2021-03-16

申请号：US16874691

申请日：2020-05-15

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Fu-Yang Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Wei-Ti Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/15 ,  H01L49/02 ,  H01L23/498

Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.

公开(公告)号：US20200273948A1

公开(公告)日：2020-08-27

申请号：US16874691

申请日：2020-05-15

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Fu-Yang Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Wei-Ti Lin

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/498 ,  H01L23/532 ,  H01L23/15

Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.

公开(公告)号：US10700161B2

公开(公告)日：2020-06-30

申请号：US16159726

申请日：2018-10-15

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Fu-Yang Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Wei-Ti Lin

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/498 ,  H01L23/15 ,  H01L23/532

Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.

公开(公告)号：US10685922B2

公开(公告)日：2020-06-16

申请号：US16240806

申请日：2019-01-07

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Yu-Hua Chen ,  Tzyy-Jang Tseng ,  Ra-Min Tain

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.