公开(公告)号：US20010029058A1

公开(公告)日：2001-10-11

申请号：US09867928

申请日：2001-05-30

Applicant: Eastman Kodak Company

Inventor： Joseph Jech JR. ,  John A. Lebens ,  John C. Brazas JR. ,  Marek W. Kowarz

IPC: H01L021/00 ,  H01L031/0232

CPC classification number: B81C1/00611 ,  B81C2201/0121

Abstract: A method for producing optically planar surfaces for micro-electromechanical system devices (MEMS), comprising the steps of: depositing a first layer over a substrate; forming a channel in the first layer wherein the channel has a depth defined by a thickness of the first layer and a width greater than 10 microns; depositing a second layer over the first layer wherein the second layer has a thickness greater than the depth of the channel and is composed of a different material than the first layer; removing the second layer from outside the channel leaving an overlap at the edge of the channel; and polishing the second layer that fills the channel to obtain an optically planar surface for the MEMS device.

Abstract translation: 一种用于制造用于微机电系统装置（MEMS）的光学平面的方法，包括以下步骤：在衬底上沉积第一层; 在第一层中形成通道，其中通道具有由第一层的厚度和大于10微米的宽度限定的深度; 在所述第一层上沉积第二层，其中所述第二层的厚度大于所述沟道的深度，并且由与所述第一层不同的材料构成; 从所述通道外部移除所述第二层，在所述通道的边缘处留下重叠; 并抛光填充通道的第二层以获得用于MEMS器件的光学平面表面。

公开(公告)号：WO2016131657A1

公开(公告)日：2016-08-25

申请号：PCT/EP2016/052318

申请日：2016-02-03

Applicant: MEMJET TECHNOLOGY LIMITED

Inventor： NORTH, Angus ,  O'REILLY, Ronan ,  MCAVOY, Gregory

IPC: B41J2/16 ,  B81C1/00

CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

Abstract translation: 一种用于填充限定在晶片衬底的前表面中的一个或多个蚀刻孔的工艺。 该方法包括以下步骤：（i）将热塑性第一聚合物层沉积到前表面和每个孔中; （ii）回流第一聚合物; （iii）将晶片衬底暴露于受控氧化等离子体; （iv）任选地重复步骤（i）至（iii）; （v）沉积可光成像的第二聚合物层; （vi）使用曝光和显影从所述孔的外周边区域选择性地除去所述第二聚合物; 和（vii）平面化前侧表面以提供填充有彼此不同的第一和第二聚合物的塞子的孔。 每个插头具有与前侧表面共面的相应的上表面。

公开(公告)号：WO2005082774A3

公开(公告)日：2005-12-22

申请号：PCT/US2005005272

申请日：2005-02-17

Applicant: WIRELESS MEMS INC ,  CHOU CHIA-SHING

Inventor： CHOU CHIA-SHING

IPC: B44C1/22 ,  B81B3/00 ,  B81C1/00 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01H1/00 ,  H01H51/22 ,  H01H57/00 ,  H01H59/00 ,  H01L21/00 ,  H01L31/00 ,  H01P1/10

CPC classification number: B81C1/00611 ,  B81C2201/0121 ,  H01H59/0009 ,  H01H2059/0072 ,  Y10T29/49105

Abstract: A method for pseudo-planarization of an electromechanical device and for forming a durable metal contact on the electromechanical device and devices formed by the method are presented. The method comprises acts of depositing various layers forming a semiconductor device. Two principal aspects of the method include the formation of a planarized dielectric/conductor layer on a substrate and the formation of an electrode in an armature of a microelectromechanical switch, with the electrode formed such that it interlocks a structural layer of the armature to ensure it remains fixed to the armature over a large number of cycles. The present invention also relates to a system and method for making MEM switches having a common ground plane. One method for making MEM switches includes: patterning a common ground plane layer on a substrate; forming a dielectric layer on the common ground plane layer; depositing a DC electrode region through the dielectric layer to contact the common ground plane layer; and depositing a conducting layer on the DC electrode region so that regions of the conducting layer contact the DC electrode region, so that the common ground plane layer provides a common ground for the regions of the conducting layer.

Abstract translation: 提出了一种用于机电装置的伪平面化和用于在机电装置上形成耐用的金属接触的方法和由该方法形成的装置。 该方法包括沉积形成半导体器件的各种层的动作。 该方法的两个主要方面包括在基板上形成平坦化的介质/导体层，以及在微机电开关的电枢中形成电极，其中电极形成为使得衔铁的结构层互锁以确保其 在大量循环中保持固定在电枢上。 本发明还涉及一种用于制造具有共同接地层的MEM开关的系统和方法。 制造MEM开关的一种方法包括：在衬底上图形化公共接地层; 在公共接地层上形成介电层; 通过所述电介质层沉积DC电极区域以接触所述公共接地层; 以及在所述直流电极区域上沉积导电层，使得所述导电层的区域与所述直流电极区域接触，使得所述公共接地层提供所述导电层的区域的公共接地。

公开(公告)号：WO2013175396A1

公开(公告)日：2013-11-28

申请号：PCT/IB2013/054169

申请日：2013-05-21

Applicant: BASF SE ,  BASF SCHWEIZ AG ,  BASF (CHINA) COMPANY LIMITED

Inventor： NOLLER, Bastian Marten ,  GILLOT, Christophe ,  FRANZ, Diana

IPC: C09G1/02 ,  H01L21/304 ,  H01L21/306

CPC classification number: C09G1/02 ,  B81C2201/0121 ,  B81C2201/0123 ,  B81C2201/0126 ,  H01L21/02024 ,  H01L21/302 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/461

Abstract: A process for the manufacture of semiconductor devices comprising the chemical-mechanical polishing of a substrate or layer containing at least one lll-V material in the presence of a chemical-mechanical polishing composition (Q1) comprising (A) inorganic particles, organic particles, or a mixture or composite thereof, (B) at least one amphiphilic non-ionic surfactant having (b1) at least one hydrophobic group; and (b2) at least one hydrophilic group selected from the group consisting of polyoxyalkylene groups comprising (b22) oxyalkylene monomer units other than oxyethylene monomer units; and (M) an aqueous medium.

Abstract translation: 一种用于制造半导体器件的方法，包括在化学机械抛光组合物（Q1）的存在下对包含至少一种III-V材料的基底或层进行化学机械抛光，所述化学机械抛光组合物包含（A）无机颗粒，有机颗粒， 或其混合物或复合物，（B）至少一种具有（b1）至少一个疏水基团的两亲性非离子表面活性剂; 和（b2）至少一种选自包含（b22）氧化烯单体单元以外的氧化烯单体单元的聚氧化烯基的亲水基团; 和（M）水性介质。

公开(公告)号：WO2005082774A2

公开(公告)日：2005-09-09

申请号：PCT/US2005/005272

申请日：2005-02-17

Applicant: WIRELESS MEMS INCORPORATED ,  CHOU, Chia-Shing

Inventor： CHOU, Chia-Shing

IPC: B81B3/00

CPC classification number: B81C1/00611 ,  B81C2201/0121 ,  H01H59/0009 ,  H01H2059/0072 ,  Y10T29/49105

Abstract: A method for pseudo-planarization of an electromechanical device and for forming a durable metal contact on the electromechanical device and devices formed by the method are presented. The method comprises acts of depositing various layers forming a semiconductor device. Two principal aspects of the method include the formation of a planarized dielectric/conductor layer on a substrate and the formation of an electrode in an armature of a microelectromechanical switch, with the electrode formed such that it interlocks a structural layer of the armature to ensure it remains fixed to the armature over a large number of cycles. The present invention also relates to a system and method for making MEM switches having a common ground plane. One method for making MEM switches includes: patterning a common ground plane layer on a substrate; forming a dielectric layer on the common ground plane layer; depositing a DC electrode region through the dielectric layer to contact the common ground plane layer; and depositing a conducting layer on the DC electrode region so that regions of the conducting layer contact the DC electrode region, so that the common ground plane layer provides a common ground for the regions of the conducting layer.

Abstract translation: 提出了一种用于机电装置的伪平面化和用于在机电装置上形成耐用的金属接触的方法和由该方法形成的装置。 该方法包括沉积形成半导体器件的各种层的动作。 该方法的两个主要方面包括在基板上形成平坦化的介质/导体层，以及在微机电开关的电枢中形成电极，其中电极形成为使得衔铁的结构层互锁以确保其 在大量循环中保持固定在电枢上。 本发明还涉及一种用于制造具有共同接地层的MEM开关的系统和方法。 制造MEM开关的一种方法包括：在衬底上图形化公共接地层; 在公共接地层上形成介电层; 通过所述电介质层沉积DC电极区域以接触所述公共接地层; 以及在所述直流电极区域上沉积导电层，使得所述导电层的区域与所述直流电极区域接触，使得所述公共接地层提供所述导电层的区域的公共接地。

公开(公告)号：EP3259134B1

公开(公告)日：2018-08-08

申请号：EP16702736.6

申请日：2016-02-03

Applicant: Memjet Technology Limited

Inventor： NORTH, Angus ,  O'REILLY, Ronan ,  MCAVOY, Gregory

IPC: B41J2/16 ,  B81C1/00

CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

公开(公告)号：EP2852644A4

公开(公告)日：2016-04-06

申请号：EP13794728

申请日：2013-05-21

Applicant: BASF SE

Inventor： NOLLER BASTIAN MARTEN ,  GILLOT CHRISTOPHE ,  FRANZ DIANA ,  LI YUZHUO

IPC: H01L21/306 ,  C09G1/02

CPC classification number: C09G1/02 ,  B81C2201/0121 ,  B81C2201/0123 ,  B81C2201/0126 ,  H01L21/02024 ,  H01L21/302 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/461

公开(公告)号：EP1568657A3

公开(公告)日：2006-07-26

申请号：EP05251031.0

申请日：2005-02-23

Applicant: The Queen's University of Belfast

Inventor： Douglas, Connor David ,  Pollard, Robert James

IPC: B81C1/00 ,  G11B5/855

CPC classification number: B81C1/00611 ,  B81C2201/0121 ,  B82Y10/00 ,  B82Y30/00 ,  G11B5/7325 ,  G11B5/85 ,  G11B5/855

Abstract: A method of disposing a plurality of isolated particles of a first material onto a substrate comprising the steps of:

(a) depositing a first species onto the substrate;
(b) anodizing the first species to produce a second species;
(c) altering the surface of the second species so that at least one first region of the second species is of greater thickness than at least one second region of the second species;
(d) depositing the first material onto the second species; and
(e) levelling the surface of the first material and the second species.

公开(公告)号：US09976983B2

公开(公告)日：2018-05-22

申请号：US14200148

申请日：2014-03-07

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yi-Hsien Chang ,  Chun-Ren Cheng

IPC: G01N27/447 ,  H01L21/768 ,  B81C1/00 ,  B01L3/00

CPC classification number: G01N27/447 ,  B01L3/502707 ,  B01L3/502792 ,  B01L2300/161 ,  B81B2203/04 ,  B81C1/00126 ,  B81C2201/0121

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an electro-wetting-on-dielectric (EWOD) device. The EWOD device includes a top portion over a bottom portion and a channel gap between the top portion and the bottom portion. The bottom portion includes a driving dielectric layer over a first electrode, a second electrode and a first separating portion of an ILD layer between the first electrode and a second electrode. The driving dielectric layer has a first thickness less than about 1,000 Å. An EWOD device with a driving dielectric layer having a first thickness less 1000 Å requires a lower applied voltage to alter a shape of a droplet within the device and has a longer operating life than an EWOD device that requires a higher applied voltage to alter the shape of the droplet.

公开(公告)号：US09969613B2

公开(公告)日：2018-05-15

申请号：US13861620

申请日：2013-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Brigham ,  Christopher V. Jahnes ,  Cameron E. Luce ,  Jeffrey C. Maling ,  William J. Murphy ,  Anthony K. Stamper ,  Eric J. White

IPC: B81C1/00 ,  G06F17/50 ,  B81B3/00

CPC classification number: B81C1/0015 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2207/09 ,  B81C1/00047 ,  B81C1/00269 ,  B81C1/00365 ,  B81C1/00531 ,  B81C1/00936 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0121 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0714 ,  G06F17/5009

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.