公开(公告)号：KR1020020050442A

公开(公告)日：2002-06-27

申请号：KR1020000079591

申请日：2000-12-21

Applicant: 엘지디스플레이 주식회사

Inventor： 신천기

IPC: H03M1/46

CPC classification number: H03M1/34 ,  H03M2201/6107 ,  H03M2201/622

Abstract: PURPOSE: An A/D(Analog/Digital) converter circuit and a method for converting an analog signal into a digital signal are provided, which reduces a conversion time and improves a conversion accuracy, by measuring only bits of high error among the whole bits according as converting the analog signal into the digital signal. CONSTITUTION: A MUX part(21) selects and outputs an inputted analog signal, and a comparator part(22) compares an output of the above MUX part with a reference signal. A microprocessor(23) outputs a digital signal of plural bits where only bits sensitive to noise are converted among digital signals of plural bits corresponding to the analog signal inputted according to the comparison result of the comparator part. And a digital/analog converter part(24) converts the digital signal being output from the microprocessor into an analog signal and then transfers it as a reference signal of the comparator part.

Abstract translation: 目的：提供A / D（模拟/数字）转换器电路和将模拟信号转换为数字信号的方法，通过仅测量整个位中的高误差位，减少转换时间并提高转换精度 根据将模拟信号转换为数字信号。 构成：MUX部分（21）选择并输出输入的模拟信号，比较器部分（22）将上述MUX部分的输出与参考信号进行比较。 微处理器（23）根据比较器部分的比较结果输出多个比特的数字信号，其中只有对噪声敏感的位被转换成与根据输入的模拟信号相对应的多个位的数字信号。 并且数字/模拟转换器部分（24）将从微处理器输出的数字信号转换为模拟信号，然后将其作为比较器部分的参考信号传送。

公开(公告)号：KR1020000056749A

公开(公告)日：2000-09-15

申请号：KR1019990006345

申请日：1999-02-25

Applicant: 에스케이하이닉스 주식회사

Inventor： 장미경

IPC: H03M1/12

CPC classification number: H03M1/204 ,  H03M2201/622

Abstract: PURPOSE: An analog/digital converter is provided to prevent increase of linear errors by the gain differential while generating folding signals, and restrain errors at the time of analog/digital conversion even if the speed of analog input is high because the number of a track/hold amplifier does not increase. CONSTITUTION: An analog/digital transformer includes followings. N number of track/hold amplifiers(61a-61n) tracks and holds voltage distributed by resistances connected in parallel and analog input (Ain) signals. A folding preprocessing block(62) generates the tracked and held signals generated from the track/hold amplifiers(61a-61n) after interpolation by 2x. A folding block(63) folds and outputs the LSB output value of the folding preprocessing block(62) generated to each folding block. A coarse preprocessing block(65) processes and outputs the folding preprocessed MSB values.

Abstract translation: 目的：提供模拟/数字转换器，以防止生成折叠信号时由增益差异引起的线性误差增加，并且即使模拟输入的速度高，因为模拟/数字转换时的误差，因为轨道的数量 /保持放大器不增加。 构成：模拟/数字变压器包括以下内容。 N个轨道/保持放大器（61a-61n）跟踪并保持由并联连接的电阻和模拟输入（Ain）信号分配的电压。 折叠预处理块（62）在内插后产生由轨道/保持放大器（61a-61n）产生的被跟踪和保持的信号。 折叠块（63）折叠并输出生成到每个折叠块的折叠预处理块（62）的LSB输出值。 粗预处理块（65）处理并输出折叠预处理的MSB值。

公开(公告)号：KR1020140047200A

公开(公告)日：2014-04-22

申请号：KR1020120111242

申请日：2012-10-08

Applicant: (주)참케어

Inventor： 이동화

IPC: H03M1/12

CPC classification number: H03M1/34 ,  H03M1/129 ,  H03M2201/61 ,  H03M2201/6157 ,  H03M2201/622 ,  H03M2201/932

Abstract: The present invention discloses an analog-to-digital converting system capable of accurate conversion even if the peak-to-peak voltage of an analog signal is low. The analog-to-digital converting system according of the present invention is configured to include an amplification part (210), an analog-to-digital converter (ADC) (220), an integrator (230), an attenuator (240), and a digital-to-analog converter (DAC) (250). The analog-to-digital converting system and converting method according to the present invention has the advantage of generating a digital signal with accuracy and a high resolution even when the peak-to-peak voltage of the analog signal is low.

Abstract translation: 本发明公开了即使模拟信号的峰 - 峰电压低的能够进行精确转换的模数转换系统。 根据本发明的模拟 - 数字转换系统被配置为包括放大部分（210），模数转换器（ADC）（220），积分器（230），衰减器（240） 和数模转换器（DAC）（250）。 根据本发明的模数转换系统和转换方法具有即使在模拟信号的峰 - 峰电压低的情况下也产生具有精度和高分辨率的数字信号的优点。

公开(公告)号：KR1020130013827A

公开(公告)日：2013-02-06

申请号：KR1020110075673

申请日：2011-07-29

Applicant: 김도율

Inventor： 조해성

IPC: H03M1/12

CPC classification number: H03M1/0607 ,  H03M1/12 ,  H03M2201/615 ,  H03M2201/622

Abstract: PURPOSE: A method of minimizing digital peak is provided to ignore meaningless peak which is mostly not recognized to people, thereby secure large gain corresponding to environment. CONSTITUTION: Gain is set up as the predetermined first gain level(S11). Generation of peak is sensed during an analog-digital conversion process(S12). Necessity of reducing the gain is determined by inspecting the peak generation(S13,S14). When necessity of the gain reduction is determined, the gain is decreased to the predetermined gain regulation width in the second gain level, which is lower than the first gain level(S15). Until gain reduction is decided to be unnecessary, the steps are repetitively performed. [Reference numerals] (S11) Setting up gain as a first gain level; (S12) Sensing the generation of peak; (S13) Checking a gain control policy by the sensed peak generation information; (S14) Determining the necessity of controlling the gain; (S15) Reducing the gain as a second gain level; (S16) Maintaining the set gain

Abstract translation: 目的：提供一种最小化数字峰值的方法来忽略大多数人不认识的无意义峰值，从而确保与环境相对应的大增益。 构成：增益设定为预定的第一增益电平（S11）。 在模拟数字转换处理期间感测到峰值的产生（S12）。 通过检查峰值生成来确定降低增益的必要性（S13，S14）。 当确定增益减小的必要性时，增益降低到低于第一增益电平的第二增益电平中的预定增益调节宽度（S15）。 直到减少增益被决定为不必要，重复执行这些步骤。 （附图标记）（S11）将增益设定为第一增益水平; （S12）感测峰的产生; （S13）通过感测到的峰值生成信息来检查增益控制策略; （S14）确定控制增益的必要性; （S15）将增益减小为第二增益电平; （S16）维持设定增益

公开(公告)号：KR1020120122899A

公开(公告)日：2012-11-07

申请号：KR1020120040135

申请日：2012-04-18

Applicant: 인터실 아메리카스 엘엘씨

Inventor： 키담비,선더에스. ,  해리스,브래논

IPC: H03M1/12

CPC classification number: H03M1/121 ,  H03M1/0624 ,  H03M1/36 ,  H03M2201/1109 ,  H03M2201/2216 ,  H03M2201/622 ,  H03M2201/6309

Abstract: PURPOSE: A multiplier-free algorithm for estimating sample-time and a gain mismatch error in a two-channel time-interleaved analog to digital converter are provided to deduct an absolute value of an output from two ADCs using a gain mismatch error estimation algorithm. CONSTITUTION: An input signal is converted into first and second digital signals with two time-leaved analog digital converter cores in order to provide a set of two ADC outputs. At least one of the two time-leaved analog digital converter cores has a correction input. The first and second digital signals are interleaved in order to form an expression of being converted into a digital format of the input signal. An error is estimated using a code value which is determined from the first and second digital signals. The correction signal is determined from the error. The correction signal is applied one or more correction input of the two time-leaved analog digital converter cores. [Reference numerals] (AA,DD) Spectrum of a signal having a sample-time mismatch error; (BB) Size(dB); (CC) Frequency(Hz)

Abstract translation: 目的：提供一种用于估计采样时间和双通道时间交织模数转换器中的增益失配误差的无乘数算法，以使用增益失配误差估计算法从两个ADC中扣除输出的绝对值。 构成：输入信号被转换成具有两个时间离散的模拟数字转换器内核的第一和第二数字信号，以提供一组两个ADC输出。 两个有时间的模拟数字转换器核心中的至少一个具有校正输入。 交织第一和第二数字信号以形成被转换为输入信号的数字格式的表达式。 使用从第一和第二数字信号确定的代码值来估计误差。 校正信号由误差确定。 校正信号被应用于两个时间上的模拟数字转换器核的一个或多个校正输入。 （参考数字）（AA，DD）具有采样时间失配误差的信号的频谱; （BB）尺寸（dB）; （CC）频率（Hz）

公开(公告)号：KR1020020018315A

公开(公告)日：2002-03-08

申请号：KR1020000051570

申请日：2000-09-01

Applicant: 엘지이노텍 주식회사

Inventor： 김건영

IPC: H03M1/66

CPC classification number: H03M1/822 ,  H03M2201/622

Abstract: PURPOSE: A digital/analog converter is provided to obtain stable an analog signal without using an exclusive semiconductor circuit for converting a digital signal to the analog signal. CONSTITUTION: A microprocessor(301) outputs a square wave signal to an input terminal of a switching portion(302). The switching portion(302) is formed by a field effect transistor. A gate of the switching portion(302) is connected with an output terminal of the microprocessor(301). A drain of the switching portion(302) is connected with a reference voltage setup portion(303). A current limit portion(303a) is connected between the reference voltage setup portion(303) and the switching portion(302). A source of the switching portion(302) is connected with a ground portion(304) for signal line. An output signal of the switching portion(302) is connected with an analog conversion circuit(305). The analog conversion circuit(305) has a low pass filter.

Abstract translation: 目的：提供数字/模拟转换器以获得稳定的模拟信号，而不使用用于将数字信号转换为模拟信号的专用半导体电路。 构成：微处理器（301）将方波信号输出到切换部分（302）的输入端。 开关部分（302）由场效应晶体管形成。 开关部分（302）的栅极与微处理器（301）的输出端连接。 开关部（302）的漏极与基准电压设定部（303）连接。 电流限制部分（303a）连接在参考电压建立部分（303）和开关部分（302）之间。 开关部分（302）的源极与用于信号线的接地部分（304）连接。 开关部分（302）的输出信号与模拟转换电路（305）连接。 模拟转换电路（305）具有低通滤波器。

公开(公告)号：KR1020000061732A

公开(公告)日：2000-10-25

申请号：KR1019990011008

申请日：1999-03-30

Applicant: 현대반도체 주식회사

Inventor： 이상대

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M2201/6107 ,  H03M2201/622

Abstract: PURPOSE: An analog/digital converter is provided to improve accuracy of conversion and arbitrarily change conversion output data by adding a logic and memory area which idealize converted output data before reading it. CONSTITUTION: An analog/digital converter includes a second output data storage register(20) for receiving an output value stored in a first output data storage register(17) according to a conversion control register(10) to temporarily store it, and an encoder and address generator(21) for receiving the data stored in the second output data storage register and encoding it to generate an address in accordance with the encoded data. There are also included an ideal data storage(22) for comparing the data of the first output data storage register with ideal data to previously store a correction value depending on the compared result and receiving the address signal from the encoder and address generator to read data of the address region, and a third output data storage register(23) for receiving the corrected data of the ideal data storage according to a setup mode of the conversion control register to temporarily store it and then outputting it to an internal data bus.

Abstract translation: 目的：提供模拟/数字转换器，以提高转换的精度，并通过添加在读取转换后的输出数据的理想化逻辑和存储区域来任意更改转换输出数据。 构成：模拟/数字转换器包括第二输出数据存储寄存器（20），用于根据转换控制寄存器（10）接收存储在第一输出数据存储寄存器（17）中的输出值，以临时存储它;以及编码器 和地址发生器（21），用于接收存储在第二输出数据存储寄存器中的数据并对其进行编码，以根据编码数据产生一个地址。 还包括用于将第一输出数据存储寄存器的数据与理想数据进行比较的理想数据存储器（22），以根据比较结果预先存储校正值，并从编码器和地址生成器接收地址信号以读取数据 和第三输出数据存储寄存器（23），用于根据转换控制寄存器的设置模式接收理想数据存储器的校正数据，以临时存储，然后将其输出到内部数据总线。

公开(公告)号：KR101160962B1

公开(公告)日：2012-06-29

申请号：KR1020110040171

申请日：2011-04-28

Applicant: 서강대학교산학협력단

Inventor： 이승훈 ,  구병우 ,  박혜림

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/0607 ,  H03M1/361 ,  H03M2201/2216 ,  H03M2201/61 ,  H03M2201/622 ,  H03M2201/643

Abstract: PURPOSE: An ADC(Analog To Digital Converter) for processing wideband variable input signals is provided to adopt all WUXGA(Wide Ultra Extended Graphics Array) resolutions from VGA(Video Graphics Array) by applying a second stage reference voltage selection method to a flash ADC. CONSTITUTION: A SHA(Sample-And-Hold Amplifier)(110) exactly samples values which are suitable for necessary specification by using GBC(Gate-Bootstrapping Circuit). A MDAC(Multiplying Digital-To-Analog Converter)(120) reduces the necessary number of unit capacitors by half since a merged-capacitor switching technique is applied. A FLASH1 ADC(Analog To Digital Converter)(130) and a FLASH2 ADC(140) apply an interpolation method. An on-chip reference current voltage generator(150) processes a broadband variable input signal through one external signal. A clock generator(160) generates non-overlapped two clocks from one reference clock, which is inputted from the outside, in a chip. A digital correction circuit(170) including the clock generator and a divider is integrated with an on-chip.

Abstract translation: 目的：提供用于处理宽带可变输入信号的ADC（模/数转换器），以通过将第二级参考电压选择方法应用于闪存ADC来采用VGA（视频图形阵列）中的所有WUXGA（Wide Ultra Extended Graphics Array） 。 构成：SHA（采样保持放大器）（110）通过使用GBC（栅极引导电路）精确地采样适合于必要规格的值。 使用合并电容切换技术，MDAC（乘法数模转换器）（120）将必需数量的单位电容器减少了一半。 FLASH1 ADC（模数转换器）（130）和FLASH2 ADC（140）应用插值方法。 片上参考电流电压发生器（150）通过一个外部信号处理宽带可变输入信号。 时钟发生器（160）从芯片中从外部输入的一个参考时钟产生非重叠的两个时钟。 包括时钟发生器和分频器的数字校正电路（170）与片上集成。

公开(公告)号：KR1020100080661A

公开(公告)日：2010-07-12

申请号：KR1020090000052

申请日：2009-01-02

Applicant: 한양대학교 산학협력단

Inventor： 유창식 ,  조준기 ,  최우석

IPC: H03M1/12 ,  H03M1/66

CPC classification number: H03M1/0619 ,  H03M1/12 ,  H03M2201/6157 ,  H03M2201/622 ,  H03M2201/718

Abstract: PURPOSE: An analog to digital converter for high speed conversion is provided to minimize errors when an analog signal is converted into a digital signal and improve a nonlinear property. CONSTITUTION: An integrating part(200) integrates a difference between an input signal and an converted analog value which is converted from a digital output signal. A pre amplifying part(210) amplifies a difference between the output signal of the integrating part and a reference voltage. A shift controlling part(250) forms a shift control signal based on a digital output signal. A digital to analog converter(260) changes a digital output signal into an analog signal and forms a difference between the converted analog signal and the input signal.

Abstract translation: 目的：提供一种用于高速转换的模/数转换器，用于在将模拟信号转换为数字信号并改善非线性特性时将误差降至最小。 构成：积分部分（200）积分输入信号和从数字输出信号转换的转换的模拟值之间的差异。 预放大部分（210）放大积分部分的输出信号和参考电压之间的差。 变速控制部（250）基于数字输出信号形成换档控制信号。 数模转换器（260）将数字输出信号改变为模拟信号，并在转换的模拟信号和输入信号之间形成差值。

公开(公告)号：KR1020070017048A

公开(公告)日：2007-02-08

申请号：KR1020060073630

申请日：2006-08-04

Applicant: 산요덴키가부시키가이샤

Inventor： 오니시아끼노부

IPC: H03M1/12 ,  H03H19/00

CPC classification number: H03M3/356 ,  H03H19/00 ,  H03M3/43 ,  H03M3/456 ,  H03M2201/61 ,  H03M2201/622

Abstract: 적분기의 적분 정밀도 및 Δ∑ 변조 회로의 변조 정밀도를 향상시켜, Δ∑ 변조형 AD 컨버터에서의 왜율 열화를 억제한다. 제1∼제4 스위치를 갖는 스위치드 캐패시터를 이용하여 구성되는 적분기의 상기 제2 및 제3 스위치와, 상기 제1 및 제4 스위치를 상보적으로 온오프하는 스위치 제어 회로로서, 상기 제1 및 제4 스위치를 오프 상태, 상기 제2 및 제3 스위치를 온 상태로 할 때에는, 상기 제4 스위치를 오프 상태로 하기 전에, 상기 제2 스위치를 온 상태로 한다.
오디오 기기, Δ∑ 변조 회로, AD 컨버터, 적분기, 양자화기