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公开(公告)号：AU2019376835B2
公开(公告)日：2022-09-29
申请号：AU2019376835
申请日：2019-11-05
Applicant: IBM
Inventor： GIAMEI BRUCE CONRAD , RECKTENWALD MARTIN , SCHMIDT DONALD WILLIAM , SLEGEL TIMOTHY , PURANIK ADITYA NITIN , FARRELL MARK , JACOBI CHRISTIAN , BRADBURY JONATHAN , ZOELLIN CHRISTIAN GERHARD
Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.
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公开(公告)号：ZA202104999B
公开(公告)日：2022-08-31
申请号：ZA202104999
申请日：2021-07-15
Applicant: IBM
Inventor： GIAMEI BRUCE CONRAD , KLEIN MATTHIAS , SLEGEL TIMOTHY , FARRELL MARK , SOFIA ANTHONY THOMAS , WEISHAUPT SIMON , MISHRA ASHUTOSH
Abstract: A DEFLATE Conversion Call general-purpose processor instruction. An instruction is obtained by a general-purpose processor of the computing environment. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes transforming, based on a function to be performed by the instruction being a compression function or a decompression function, state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data. The transformed state of the data is provided as output to be used in performing a task.
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公开(公告)号：CA2940905C
公开(公告)日：2022-08-16
申请号：CA2940905
申请日：2015-03-19
Applicant: IBM
Inventor： GREINER DAN , FARRELL MARK , OSISEK DAMIAN LEO , SCHMIDT DONALD WILLIAM , BUSABA FADI YUSUF , KUBALA JEFFREY PAUL , BRADBURY JONATHAN DAVID , HELLER LISA CRANTON , SLEGEL TIMOTHY , GAINEY CHARLES , JACOBI CHRISTIAN
Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.
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公开(公告)号：ZA202103133B
公开(公告)日：2022-07-27
申请号：ZA202103133
申请日：2021-05-10
Applicant: IBM
Inventor： GIAMEI BRUCE CONRAD , RECKTENWALD MARTIN , SCHMIDT DONALD WILLIAM , SLEGEL TIMOTHY , PURANIK ADITYA NITIN , FARRELL MARK , JACOBI CHRISTIAN , BRADBURY JONATHAN , ZOELLIN CHRISTIAN GERHARD
Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.
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公开(公告)号：ZA201902529B
公开(公告)日：2022-04-28
申请号：ZA201902529
申请日：2019-04-23
Applicant: IBM
Inventor： COPELAND REID , MUELLER SILVIA MELITTA , BRADBURY JONATHAN , SLEGEL TIMOTHY
Abstract: An instruction to perform a sign operation of a plurality of sign operations configured for the instruction. The instruction is executed, and the executing includes selecting at least a portion of an input operand as a result to be placed in a select location. The selecting is based on a control of the instruction, in which the control indicates a user-defined size of the input operand to be selected as the result. A sign of the result is determined based on a plurality of criteria, including a value of the result, obtained based on the control of the instruction, having a first particular relationship or a second particular relationship with respect to a selected value. The result and the sign are stored in the select location to provide a signed output to be used in processing within the computing environment.
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Patent Agency Ranking
公开(公告)号：BR112014031335B1
公开(公告)日：2022-01-04
申请号：BR112014031335
申请日：2012-11-22
Applicant: IBM
Inventor： JACOBI CHRISTIAN , GREINER DAN , MITRAN MARCEL , SLEGEL TIMOTHY
IPC: G06F11/07
Abstract: bloco de diagnóstico transacional. quando um abortar de uma operação ocorre num sistema de computador, e feita uma determinação para saber se a informação de diagnostico e para ser armazenado em um ou mais blocos de diagnostico de transação (tdbs). existem diferentes tipos de blocos de diagnostico de transação para aceitar informação de diagnostico, dependendo do tipo de abortar e outras considerações. como exemplos, ha uma tdb especificada pelo programa em que a informação e armazenada se um endereço valido tdb e fornecido em uma transação começar a instrução; tdb uma interrupção de programa, que e armazenado em, quando o programa e abortado devido a uma interrupção; e uma tdb interceptação programa, que e armazenado em um aborto quando resulta em uma interceptação.
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公开(公告)号：DK3571578T3
公开(公告)日：2021-09-27
申请号：DK17797326
申请日：2017-11-09
Applicant: IBM
Inventor： GREINER DAN , SAPORITO ANTHONY , SHUM CHUNG-LUNG , SLEGEL TIMOTHY , JACOBI CHRISTIAN
IPC: G06F9/30
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公开(公告)号：SG11202105494SA
公开(公告)日：2021-06-29
申请号：SG11202105494S
申请日：2020-02-20
Applicant: IBM
Inventor： KLEIN MATTHIAS , GIAMEI BRUCE , SOFIA ANTHONY , FARRELL MARK , SWANEY SCOTT , SLEGEL TIMOTHY
IPC: G06F9/455
Abstract: A system is provided and includes a plurality of machines. The plurality of machines includes a first generation machine and a second generation machine. Each of the plurality of machines includes a machine version. The first generation machine executes a first virtual machine and a virtual architecture level. The second generation machine executes a second virtual machine and the virtual architecture level. The virtual architecture level provides a compatibility level for a complex interruptible instruction to the first and second virtual machines. The compatibility level is architected for a lowest common denominator machine version across the plurality of machines. The compatibility level includes a lowest common denominator indicator identifying the lowest common denominator machine version.
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公开(公告)号：AU2020213853A1
公开(公告)日：2021-06-03
申请号：AU2020213853
申请日：2020-01-23
Applicant: IBM
Inventor： GIAMEI BRUCE CONRAD , KLEIN MATTHIAS , SLEGEL TIMOTHY , FARRELL MARK , SOFIA ANTHONY THOMAS , WEISHAUPT SIMON , MISHRA ASHUTOSH
IPC: G06F9/30
Abstract: A DEFLATE Conversion Call general-purpose processor instruction. An instruction is obtained by a general- purpose processor of the computing environment. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes transforming, based on a function to be performedby the instruction being a compression functionor a decompression function, state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data. The transformed state of the data is provided as output to be used in performing a task.
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公开(公告)号：LT3571594T
公开(公告)日：2021-04-26
申请号：LT18700178
申请日：2018-01-03
Applicant: IBM
Inventor： GREINER DAN , SLEGEL TIMOTHY , JACOBI CHRISTIAN , SAPORITO ANTHONY , PAPROTSKI VOLODYMYR , MITRAN MARCEL
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