公开(公告)号：US07368313B2

公开(公告)日：2008-05-06

申请号：US11053115

申请日：2005-02-07

Applicant: Hubert Benzel ,  Gerhard Lammel

Inventor： Hubert Benzel ,  Gerhard Lammel

IPC: H01L29/04

CPC classification number: B81C1/00158 ,  B81B2201/0264 ,  B81C2201/0115 ,  B81C2201/014 ,  G01L9/0042 ,  G01L9/0054

Abstract: In a method for manufacturing a micromechanical semiconductor component, e.g., a pressure sensor, a locally limited, buried, and at least partially oxidized porous layer is produced in a semiconductor substrate. A cavity is subsequently produced in the semiconductor substrate from the back, directly underneath the porous first layer, using a trench etch process. The porous first layer is used as a stop layer for the trench. Thin diaphragms having a low thickness tolerance may thus be produced for differential pressure measurement.

Abstract translation: 在制造微机电半导体部件的方法中，例如压力传感器，在半导体衬底中产生局部限制的，掩埋的和至少部分氧化的多孔层。 随后，使用沟槽蚀刻工艺，在半导体衬底中从后部直接在多孔第一层下方产生空腔。 多孔第一层用作沟槽的停止层。 因此可以产生具有低厚度公差的薄膜，用于差压测量。

公开(公告)号：US20080032501A1

公开(公告)日：2008-02-07

申请号：US11459307

申请日：2006-07-21

Applicant: Jonathan L. Klein ,  Jorg Pilchowski

Inventor： Jonathan L. Klein ,  Jorg Pilchowski

IPC: H01L21/44

CPC classification number: B81C1/00579 ,  B81C2201/0107 ,  B81C2201/014

Abstract: Micro-electromechanical systems (MEMS) pre-fabrication products and methods for forming MEMS devices using silicon-on-metal (SOM) wafers. An embodiment of a method may include the steps of bonding a patterned SOM wafer to a cover wafer, thinning the handle layer of the SOM wafer, selectively removing the exposed metal layer, and either continuing with final metallization or cover bonding to the back of the active layer.

Abstract translation: 微机电系统（MEMS）预制产品和使用金属硅（SOM）晶片形成MEMS器件的方法。 方法的一个实施例可以包括以下步骤：将图案化的SOM晶片结合到覆盖晶片，使SOM晶片的手柄层变薄，选择性地去除暴露的金属层，并且继续进行最后的金属化或覆盖粘合到 活动层

公开(公告)号：US20070166844A1

公开(公告)日：2007-07-19

申请号：US11571600

申请日：2005-06-23

Applicant: Yasuhiro Morikawa ,  Toshio Hayashi ,  Koukou Suu

Inventor： Yasuhiro Morikawa ,  Toshio Hayashi ,  Koukou Suu

IPC: H01L21/00

CPC classification number: H01L21/30655 ,  B81C1/00595 ,  B81C2201/014 ,  H01J37/3255 ,  H01J2237/334

Abstract: An etching method and an etching system are adapted to produce a high etch selectivity for a mask, an excellent anisotropic profile and a large etching depth. An etching system according to the invention comprises a floating electrode arranged vis-à-vis a substrate electrode in a vacuum chamber and held in a floating state in terms of electric potential, a material arranged at the side of the floating electrode facing the substrate electrode to form an anti-etching film and a control unit for intermittently applying high frequency power to the floating electrode. An etching method according to the invention uses a material arranged at the side of the floating electrode opposite to the substrate electrode to form an anti-etching film as target and only rare gas as main gas and is adapted to repeat a step of forming a film on the substrate by sputtering by applying high frequency power to the floating electrode and a step of subsequently etching the substrate by suspending the application of high frequency power to the floating electrode and introducing etching gas into the vacuum chamber in a predetermined sequence (FIG. 1).

Abstract translation: 蚀刻方法和蚀刻系统适于产生掩模的高蚀刻选择性，优异的各向异性轮廓和大的蚀刻深度。 根据本发明的蚀刻系统包括相对于真空室中的基板电极布置并且在电位方面保持为浮置状态的浮动电极，布置在浮置电极的面向基板电极的一侧的材料 形成抗蚀刻膜和用于间歇地向浮动电极施加高频电力的控制单元。 根据本发明的蚀刻方法使用布置在与基板电极相对的浮动电极侧的材料以形成作为目标的抗蚀刻膜，并且仅将稀有气体作为主要气体，并且适于重复形成膜的步骤 通过向浮动电极施加高频电力而通过溅射在衬底上，并且通过将浮动电极悬浮施加高频电力并以预定顺序将蚀刻气体引入真空室中，随后蚀刻衬底的步骤（图1 ）。

公开(公告)号：US07183637B2

公开(公告)日：2007-02-27

申请号：US11129541

申请日：2005-05-13

Applicant: Mike Bruner

Inventor： Mike Bruner

IPC: H01L21/00 ,  H01L21/461

CPC classification number: B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

Abstract translation: 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有覆盖层，其优选地包括氧化硅和/或氮化硅，并且其形成在耐蚀刻衬底上。 优选地包括氮化硅的图案化器件层嵌入牺牲材料中，优选地包括多晶硅，并且设置在耐蚀刻衬底和覆盖层之间。 进入沟槽或孔形成在覆盖层中，并且牺牲材料通过进入沟槽被选择性地蚀刻，使得器件层的部分从牺牲材料释放。 蚀刻剂优选包含惰性气体氟化物NGF 2X（其中Ng = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料之后，进入沟槽被密封以将器件层的释放部分封装在耐蚀刻衬底和覆盖层之间。 本发明对于制造具有多个释放特征的MEMS器件，多腔器件和器件特别有用。

公开(公告)号：US20060066932A1

公开(公告)日：2006-03-30

申请号：US11090773

申请日：2005-03-25

Applicant: Clarence Chui ,  Manish Kothari ,  Brian Gally ,  Ming-Hau Tung

Inventor： Clarence Chui ,  Manish Kothari ,  Brian Gally ,  Ming-Hau Tung

IPC: G02F1/03

CPC classification number: G02B26/001 ,  B81B2201/042 ,  B81C1/00793 ,  B81C1/00801 ,  B81C2201/014

Abstract: The fabrication of a MEMS device such as an interferometric modulator is improved by employing an etch stop layer between a sacrificial layer and a mirror layer. The etch stop may reduce undesirable over-etching of the sacrificial layer and the mirror layer. The etch stop layer may also serve as a barrier layer, buffer layer, and/or template layer.

Abstract translation: 通过在牺牲层和镜层之间采用蚀刻停止层来改善诸如干涉式调制器之类的MEMS器件的制造。 蚀刻停止可减少对牺牲层和镜层的不希望的过蚀刻。 蚀刻停止层也可以用作阻挡层，缓冲层和/或模板层。

公开(公告)号：US20060008935A1

公开(公告)日：2006-01-12

申请号：US11169583

申请日：2005-06-30

Applicant: Makoto Asai

Inventor： Makoto Asai

IPC: H01L21/306 ,  G01P15/125

CPC classification number: B81C1/00626 ,  B81B2201/0235 ,  B81B2201/0292 ,  B81B2203/0118 ,  B81C2201/014 ,  B81C2201/019 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814

Abstract: A physical quantity sensor includes: a semiconductor substrate; a cavity disposed in the substrate and extending in a horizontal direction of the substrate; a groove disposed on the substrate and reaching the cavity; a movable portion separated by the cavity and the groove so that the movable portion is movably supported on the substrate; and an insulation layer disposed on a bottom of the movable portion so that the insulation layer provides a roof of the cavity.

Abstract translation: 物理量传感器包括：半导体衬底; 设置在所述基板中并在所述基板的水平方向上延伸的空腔; 设置在所述基板上并到达所述空腔的凹槽; 可移动部分，由空腔和沟槽分隔开，使得可移动部分可移动地支撑在基板上; 以及设置在所述可动部分的底部上的绝缘层，使得所述绝缘层提供所述空腔的顶部。

公开(公告)号：US20050250235A1

公开(公告)日：2005-11-10

申请号：US11090911

申请日：2005-03-25

Applicant: Mark Miles ,  John Batey ,  Clarence Chui ,  Manish Kothari ,  Ming-Hau Tung

Inventor： Mark Miles ,  John Batey ,  Clarence Chui ,  Manish Kothari ,  Ming-Hau Tung

IPC: B81B3/00 ,  H01L21/00

CPC classification number: B81B3/0086 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2201/053 ,  G02B26/001

Abstract: In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the microelectromechanical systems device.

Abstract translation: 在一个实施例中，本发明提供一种用于制造微机电系统装置的方法。 该方法包括制造包括具有特征机电响应的膜的第一层和特征光学响应，其中特征光学响应是期望的，并且特征机电响应是不期望的; 以及通过在所述微机电系统装置的启动期间至少减少其上的电荷积累来修改所述第一层的特征机电响应。

公开(公告)号：US06787387B2

公开(公告)日：2004-09-07

申请号：US10601470

申请日：2003-06-23

Applicant: Kimiya Ikushima ,  Hiroyoshi Komobuchi ,  Mikiya Uchida

Inventor： Kimiya Ikushima ,  Hiroyoshi Komobuchi ,  Mikiya Uchida

IPC: H01L2100

CPC classification number: G01J5/20 ,  B81B3/0072 ,  B81B2201/0207 ,  B81B2203/0127 ,  B81C1/00047 ,  B81C1/00801 ,  B81C2201/0109 ,  B81C2201/014 ,  G01F1/6845 ,  G01J5/023 ,  G01J5/024 ,  G01J5/045 ,  G01J5/10 ,  G01J5/34

Abstract: A method for fabricating an electronic device includes the steps of: preparing a cavity defining sacrificial layer, at least the upper surface of which is covered with an etch stop layer; forming at least one first opening in the etch stop layer, thereby partially exposing the surface of the cavity defining sacrificial layer; etching the cavity defining sacrificial layer through the first opening, thereby defining a provisional cavity under the etch stop layer and a supporting portion that supports the etch stop layer thereon; and etching away a portion of the etch stop layer, thereby defining at least one second opening that reaches the provisional cavity through the etch stop layer and expanding the provisional cavity into a final cavity.

公开(公告)号：US20040110318A1

公开(公告)日：2004-06-10

申请号：US10725874

申请日：2003-12-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takahiro Oguchi

IPC: H01L021/00

CPC classification number: G01C19/5719 ,  B81B2201/025 ,  B81C1/00579 ,  B81C1/00587 ,  B81C2201/0132 ,  B81C2201/014 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S148/159

Abstract: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole dry etching of an element substrate, and an electrically conductive material is used as an etching stop layer during the dry etching.

Abstract translation: 通过干式蚀刻中的蚀刻停止层，使用通过元件基板的贯通孔干蚀刻形成传感器元件的外力检测传感器的制造方法。

公开(公告)号：US20040104454A1

公开(公告)日：2004-06-03

申请号：US10605585

申请日：2003-10-10

Applicant: ROHM CO., LTD.

Inventor： Masaki Takaoka ,  Noriyuki Shimoji

IPC: H01L029/40

CPC classification number: B81B3/007 ,  B81B2201/052 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81C2201/014 ,  B81C2201/019 ,  H01L23/481 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor device is disclosed which can be miniaturized and in which structures on a semiconductor substrate therein are difficult to delaminate, as well as a method of producing the same. The semiconductor device includes a semiconductor substrate main unit, and a thin portion that is thinner than the main unit and formed such that a recessed portion is formed in the semiconductor substrate and has at least one through hole formed therein. The thin portion is formed such that the etching rate of the thin portion is slower than the etching rate of the main unit. The thin portion provides a bridging structure between both sides of the recessed portion, and can mechanically and structurally strengthen the semiconductor device with respect to forces applied from the side surfaces of the main unit of the semiconductor substrate. Thus, structures such as wires, films, and semiconductor elements formed on the main unit and/or the thin portion of the semiconductor substrate or via the through holes will be difficult to detach from the semiconductor device.

Abstract translation: 公开了可以小型化并且其中的半导体衬底上的结构难以分层的半导体器件及其制造方法。 半导体器件包括半导体衬底主单元和比主单元薄的薄部分，并且形成为在半导体衬底中形成凹部并且在其中形成有至少一个通孔。 薄部形成为使得薄部的蚀刻速度比主体的蚀刻速度慢。 薄壁部分在凹部的两侧之间提供桥接结构，并且可相对于从半导体衬底的主单元的侧表面施加的力来机械地和结构地加强半导体器件。 因此，形成在半导体基板的主单元和/或薄壁部分上或通过通孔的诸如导线，膜和半导体元件的结构将难以从半导体器件分离。