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    MEMORY CELL
    31.
    发明专利
    MEMORY CELL 失效

    公开(公告)号：JP2000124413A

    公开(公告)日：2000-04-28

    申请号：JP29238699

    申请日：1999-10-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： JEROME SUIAVATI ,  CHRISTIAN BOCCASIO

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: PROBLEM TO BE SOLVED: To simplify a manufacturing method of a DRAM cell by depositing a third conductive layer on a second insulation film after a second opening is formed. SOLUTION: For example, a DRAM cell is formed in an integrated circuit. While on the one hand a capacitor with an electrode in contact with a first region 2-1 in a substrate 1 is formed, on the other hand a contact with a semiconductor region 2-2 in the substrate 1 is formed. That is, an insulator thickness A between the substrate 1 and a third conductive layer 17 is selected to be between a thickness D1 of a first insulation layer 13-1 and a thickness E1 of a second insulation layer 13-2 and to make an upper surface of a second electrode 16 practically flush with an upper surface of the conductive layer 17. Therefore, a third opening 030 and a fourth opening 040 practically have the same depth and flattening can be simplified by reducing a thickness E1 to minimize height difference of an upper surface of the insulation layer 18 between a part covering a region to establish a contact with the region 2-2 and a part covering a region to establish a contact with a second electrode of a capacitor.

    EPITAXY METHOD ON SILICON SUBSTRATE INVOLVING REGIONS HEAVILY DOPED WITH BORON
    32.
    发明专利
    EPITAXY METHOD ON SILICON SUBSTRATE INVOLVING REGIONS HEAVILY DOPED WITH BORON 失效

    公开(公告)号：JP2000124132A

    公开(公告)日：2000-04-28

    申请号：JP27435199

    申请日：1999-09-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

    IPC: H01L21/302 ,  H01L21/205 ,  H01L21/22 ,  H01L21/3065 ,  H01L21/203

    Abstract: PROBLEM TO BE SOLVED: To avoid self-doping by etching a Si substrate by a specified thickness with a silicon chloride compound gas introduced before depositing in the vapor phase epitaxial deposition on the Si substrate having high-concentration dopant regions. SOLUTION: In the vapor phase epitaxial deposition on a Si substrate 1 having dopant regions 6, 7 containing boron at a high concentration, the initial annealing is selectively made and the epitaxial deposition is made for a given time to obtain an epitaxial layer 5 having a desired usual thickness. Before the epitaxial deposition, a silicon chloride compound gas is introduced to etch the Si substrate 1 by a thickness of about 100 nm or less to thereby remove a self-doped layer of boron to the epitaxial layer 5. Thus the self-doping of boron to the epitaxial layer 5 is reduced.

    INTEGRATED CIRCUIT AND TEST STRUCTURE
    33.
    发明专利
    INTEGRATED CIRCUIT AND TEST STRUCTURE 失效

    公开(公告)号：JPH11251315A

    公开(公告)日：1999-09-17

    申请号：JP36911598

    申请日：1998-12-25

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAYET PHILIPPE ,  BRUNEL CHANTAL ,  MARTIN STEPHANE

    IPC: H01L21/3205 ,  G01R31/28 ,  G03F7/20 ,  H01L23/52 ,  H01L23/528

    Abstract: PROBLEM TO BE SOLVED: To judge resistance of a via, by a method wherein, in a position alignment between a path of a metallization layer and the corresponding via, or between the via and the corresponding path, a contact area between the path and the via is corrected with respect to a normal contact area. SOLUTION: First and second path parts 21, 22 are extended to a direction for corresponding vias 24, 25 and come close to all path parts neighboring the via on the same metallization layer from a common side. A continuous part 23 is not placed so that it comes nearer to one of the vias 24, 25 with substantially larger than a width of the via. A contact area is equal irrespective of a direction and an orientation of offsets between a path 20 and the vias 24, 25. All resistances in a part of the predetermined number of vias and paths are calculated, and a value of one via resistance can be obtained, and it is possible to uniformize more the respective via resistances in the entire integrated circuit and to judge an individual via resistance.

    IMPROVEMENT OF SINGLE CRYSTAL SILICON WAFER IN MECHANICAL RESISTANCE
    34.
    发明专利
    IMPROVEMENT OF SINGLE CRYSTAL SILICON WAFER IN MECHANICAL RESISTANCE 失效

    公开(公告)号：JPH11219873A

    公开(公告)日：1999-08-10

    申请号：JP30640998

    申请日：1998-10-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： VANDEPUTTE JACQUES ,  BOURDET FLORINE

    IPC: H01L21/304 ,  C30B33/00 ,  H01L21/02 ,  H01L29/02

    Abstract: PROBLEM TO BE SOLVED: To enable a silicon wafer to be bent without breaking it when a mechanical stress is applied to the wafer by a method wherein the wafer is lessened in thickness as prescribed so as to be flexible, and made to have a restoring force to recover from a deflection. SOLUTION: The first surface of a silicon wafer is subjected to chemical etching and mechanochemical polishing, wherein a holding device is provided to enable the silicon wafer to make an outer cycloid rotary motion to a polishing felt, and molecular adhesion is generated between the second surface of the silicon wafer and the surface of the holding device to enable the holding device to support the wafer to make the wafer as thin as below 80 μm by polishing. The silicon wafer gets flexible to have a restoring force to cover from a deflection. By this setup, integrated circuits formed of the silicon wafer can be improved in mechanical resistance.

    SWITCHING D.C. VOLTAGE CONTROL CIRCUIT
    35.
    发明专利
    SWITCHING D.C. VOLTAGE CONTROL CIRCUIT 失效

    公开(公告)号：JPH11219222A

    公开(公告)日：1999-08-10

    申请号：JP32139798

    申请日：1998-10-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： SIMONNET JEAN MICHEL

    IPC: G05F1/10 ,  G05F3/18

    Abstract: PROBLEM TO BE SOLVED: To improve voltage control characteristics in a voltage stabilizing circuit for which a semiconductor element is inserted between input/output terminals. SOLUTION: In this switching D.C. voltage control circuit provided with the input terminal, the output terminal, a reference terminal and a control terminal, a gate turn-off thyristor Th for connecting a main terminal to the input/output terminals, a resistor R connected between the input terminal and the cathode gate of the thyristor Th, a transistor for connecting the main terminal to the cathode gate of the thyristor Th and the reference terminal and an avalanche diode Z connected between the output terminal and the base of the transistor are provided.

    Resonator, and method of forming resonator
    38.
    发明专利
    Resonator, and method of forming resonator 审中-公开
    谐振器和形成谐振器的方法

    公开(公告)号：JP2010022000A

    公开(公告)日：2010-01-28

    申请号：JP2009161062

    申请日：2009-07-07

    Applicant: Commissariat A L'energie Atomique ,  St Microelectronics Sa ,  エス テ マイクロエレクトロニクス エス アー ,  コミサリア ア エナジー アトミック

    Inventor： DURAND CEDRIC ,  CASSET FABRICE

    IPC: H03H9/24 ,  B81B3/00 ,  B81C1/00 ,  H03H3/007 ,  H03H3/013

    CPC classification number: H03H9/02448 ,  H03H3/0076 ,  H03H9/2436 ,  H03H9/2463 ,  H03H2009/0237 ,  H03H2009/02496 ,  H03H2009/2442

    Abstract: PROBLEM TO BE SOLVED: To provide a resonator that overcomes a marked drop in its frequency during a rise in temperature, and to provide a method of forming the resonator. SOLUTION: The resonator is a bulk-mode resonator including a resonant element 20 that includes a bulk 21 and a columnar portion 24. The columnar portion 24 is formed of a Young's modulus material having a temperature coefficient sign of the bulk material and a temperature coefficient of an opposite sign. Furthermore, the columnar portion 24 is dispersed such that it is vertically long with respect to the vibration direction of a bulk wave, and intercepts the resonant element 20 in the expansion/compression direction of the resonant element 20 to have a continuous part of the bulk 21. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种谐振器，其在温度升高期间克服其频率的显着下降，并提供形成谐振器的方法。 解决方案：谐振器是包括谐振元件20的体模式谐振器，谐振元件20包括主体21和柱状部分24.柱状部分24由具有散装材料的温度系数符号的杨氏模量材料形成， 相反符号的温度系数。 此外，柱状部分24相对于体波的振动方向被分散成垂直长度，并且在共振元件20的膨胀/压缩方向上截获谐振元件20以具有连续部分的体积 21.版权所有（C）2010，JPO＆INPIT

    Process for automatic correction of spectral inversion in demodulator and device to implement the process
    39.
    发明专利
    Process for automatic correction of spectral inversion in demodulator and device to implement the process 有权
    用于自动校正分散器中的光谱反转的过程和实现该过程的装置

    公开(公告)号：JP2007020169A

    公开(公告)日：2007-01-25

    申请号：JP2006183340

    申请日：2006-07-03

    Applicant: St Microelectronics Sa ,  エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

    Inventor： MEYER JACQUES

    IPC: H04L27/22

    CPC classification number: H04L27/2273 ,  H03D3/00 ,  H04L27/22

    Abstract: PROBLEM TO BE SOLVED: To provide a technology capable of momentarily detecting a spectral inversion from a received signal in a pseudo way.
    SOLUTION: A process of correction of the spectral inversion for a receiver in a digital communication system: the process allows the reception in the receiver of a training sequence presumably known according to a modulation of type π/2 BPSK or MDP2. The process includes a step of demodulating the training sequence; steps (21, 22, 23) of calculating the differential correlation on a set of N received samples (R
    n ) and presumably sent samples (S
    n ) to generate a result; and a step of using the result to detect the beginning of the screen and to order a spectral inversion in the chain of reception of the aforementioned receiver before launching the detection of the beginning of the frame. The process can realize automatic process of the spectral inversion by the receiver.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种能够以伪方式从接收信号瞬时检测频谱反演的技术。 解决方案：数字通信系统中的接收机的频谱反演的校正过程：该过程允许在接收机中接收根据类型π/ 2 BPSK或MDP2可能已知的训练序列。 该过程包括解调训练序列的步骤; 计算一组N个接收样本（R SB> n ）和推测发送的样本（S n ）之间的差分相关性以产生结果的步骤（21,22,23） ; 以及在开始对帧的开始的检测之前，使用结果来检测屏幕的开始并且在上述接收器的接收链中订购频谱反转的步骤。 该过程可以实现接收机的频谱反演的自动处理。 版权所有（C）2007，JPO＆INPIT

    Optical semiconductor package equipped with a compressible adjusting means
    40.
    发明专利
    Optical semiconductor package equipped with a compressible adjusting means 审中-公开
    光学半导体封装具有可压缩的调整方式

    公开(公告)号：JP2005354039A

    公开(公告)日：2005-12-22

    申请号：JP2005121584

    申请日：2005-04-19

    Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

    Inventor： VITTU JULIEN

    IPC: G02B7/02 ,  H01L27/14 ,  H01L31/0203 ,  H01L31/0232

    CPC classification number: H01L31/0203 ,  H01L27/14618 ,  H01L31/02325 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To make it simple to fit a lens to an optical sensor in an optical semiconductor package. SOLUTION: Provided is the optical semiconductor package comprising a support with a passage to receive a ring holding a lens situated facing an optical sensor. The support (6) has, in the passage, at least one local release recess (9), and the ring (7) is equipped peripherally with a locally projecting, elastically deformable means (14). The local release recess and the elastically deformable means are such that, when the ring occupies an angular mounting position, the locally projecting means is engaged in the local recess of the support and, when the ring is swiveled from the angular mounting position, the locally projecting means is moved out of the recess of the support and is compressed against the wall of the passage in order to secure the ring relative to the support. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：为了使光学半导体封装中的光学传感器安装透镜变得简单。 解决方案：提供了一种光学半导体封装，其包括具有通道的支撑件，该通道用于接收保持面向光学传感器的透镜的环。 支撑件（6）在通道中具有至少一个局部释放凹部（9），并且环（7）在外周配备有局部突出的可弹性变形的装置（14）。 局部释放凹部和可弹性变形的装置使得当环形件处于角度安装位置时，局部突出装置接合在支撑件的局部凹部中，并且当环从角度安装位置旋转时， 突出装置从支撑件的凹部移出并被压靠在通道的壁上，以便相对于支撑件固定环。 版权所有（C）2006，JPO＆NCIPI

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