公开(公告)号：KR1020030094688A

公开(公告)日：2003-12-18

申请号：KR1020020031942

申请日：2002-06-07

Applicant: 삼성전자주식회사

Inventor： 홍은기 ,  한정남 ,  구주선

IPC: H01L21/76

Abstract: PURPOSE: A trench isolation method is provided to prevent the generation of seam or void by using a fluid insulation layer as a trench insulation layer, and to prevent recess in the trench insulation layer by eliminating a silicon nitride layer used as an etch stop layer through a selective dry etch process. CONSTITUTION: A mask layer pattern for defining an isolation region is formed on a substrate(102). The substrate is etched to form a trench by using the mask layer pattern as an etch mask. A fluid trench insulation layer(108) is formed in the trench and on the mask layer pattern. The trench insulation layer is planarized until the surface of the mask layer pattern is exposed. The mask layer pattern is removed through a selective dry etch process.

Abstract translation: 目的：提供沟槽隔离方法，以通过使用流体绝缘层作为沟槽绝缘层来防止接缝或空隙的产生，并且通过消除用作蚀刻停止层的氮化硅层来防止沟槽绝缘层中的凹陷 选择性干蚀刻工艺。 构成：在衬底（102）上形成用于限定隔离区域的掩模层图案。 通过使用掩模层图案作为蚀刻掩模来蚀刻衬底以形成沟槽。 在沟槽和掩模层图案上形成流体沟槽绝缘层（108）。 沟槽绝缘层被平坦化，直到掩模层图案的表面露出。 通过选择性干蚀刻工艺去除掩模层图案。

公开(公告)号：KR1020030069375A

公开(公告)日：2003-08-27

申请号：KR1020020008976

申请日：2002-02-20

Applicant: 삼성전자주식회사

Inventor： 홍은기 ,  박선후 ,  구주선

IPC: H01L21/3105

Abstract: PURPOSE: A method for fabricating a silicon oxide layer is provided to control consecutive oxidation of the silicon oxide layer and maintain stability of the silicon oxide layer even if time goes by through performing a plasma process using a spin-on-glass(SOG) solution when the silicon oxide layer is formed. CONSTITUTION: An SOG solution is applied to the upper surface of a substrate(10) having on which a step is formed. The SOG layer is baked to be transformed into a silicon oxide layer. The silicon oxide layer is processed by using plasma to control the variation of the etch rate of the silicon oxide layer even if time goes by.

Abstract translation: 目的：提供一种制造氧化硅层的方法，以控制氧化硅层的连续氧化并保持氧化硅层的稳定性，即使通过使用旋涂玻璃（SOG）溶液进行等离子体处理的时间过去 当形成氧化硅层时。 构成：将SOG溶液施加到其上形成有台阶的基板（10）的上表面。 烘烤SOG层以转变成氧化硅层。 通过使用等离子体来处理氧化硅层，以控制氧化硅层的蚀刻速率的变化，即使时间过去。

公开(公告)号：KR100354441B1

公开(公告)日：2002-09-28

申请号：KR1020000082829

申请日：2000-12-27

Applicant: 삼성전자주식회사

Inventor： 구주선 ,  홍은기 ,  김홍근 ,  홍진기

IPC: H01L21/316

公开(公告)号：KR1020000060956A

公开(公告)日：2000-10-16

申请号：KR1019990009655

申请日：1999-03-22

Applicant: 삼성전자주식회사

Inventor： 구주선 ,  박희숙 ,  김병준

IPC: H01L21/32

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to mitigate deterioration of the semiconductor device caused by a resistor-capacitor delay by forming an interlayer dielectric with an air gap, and to prevent the air gap from going down partially by converting an interlayer dielectric to an air gap after a chemical mechanical polishing process. CONSTITUTION: A method for manufacturing a semiconductor device comprises the steps of: sequentially forming an air gap precursor layer(34) and an air gap protection layer composed of organic polymer on a semiconductor substrate(30) having a conductive layer(32); patterning the air gap protection layer to form an opening exposing the air gap precursor layer, and forming an etching stop layer pattern(44) composed of the air gap protection layer; forming an insulating layer pattern having a damascene interconnection region exposing the opening to an upper portion of the etching stop layer pattern; etching the air gap precursor layer by using the etching stop layer pattern as a mask to form the opening exposing the conductive layer; filling the damascene interconnection region and opening with a conductive material(50); planarizing the conductive material by having an upper surface of the insulating layer pattern as a planarization end point, to form a dual damascene interconnection contacting the conductive layer; and converting the air gap precursor layer to an air gap.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过形成具有气隙的层间电介质来减轻由电阻器 - 电容器延迟引起的半导体器件的劣化，并且通过转换层间电介质来防止气隙部分下降 在化学机械抛光工艺之后到气隙。 构成：制造半导体器件的方法包括以下步骤：在具有导电层（32）的半导体衬底（30）上依次形成气隙前体层（34）和由有机聚合物构成的气隙保护层; 图案化气隙保护层以形成暴露气隙前体层的开口，以及形成由气隙保护层组成的蚀刻停止层图案（44）; 形成具有将所述开口暴露于所述蚀刻停止层图案的上部的镶嵌互连区域的绝缘层图案; 通过使用蚀刻停止层图案作为掩模蚀刻气隙前体层，以形成露出导电层的开口; 填充镶嵌互连区域并用导电材料（50）打开; 通过使绝缘层图案的上表面作为平坦化终点来平坦化导电材料，以形成接触导电层的双镶嵌互连; 并将气隙前体层转换成气隙。

公开(公告)号：KR1020000059383A

公开(公告)日：2000-10-05

申请号：KR1019990006934

申请日：1999-03-03

Applicant: 삼성전자주식회사

Inventor： 신홍재 ,  이해정 ,  구주선

IPC: H01L21/3205

Abstract: PURPOSE: A method for forming a multi layered wire structure using a LPD(liquid-phase deposition) silicone oxide layer is to minimize a parasitic capacitance generated between metal wires when forming a multi layered wire using a dual damascene process. CONSTITUTION: A method for forming a multi layered wire structure using a LPD(liquid-phase deposition) silicone oxide layer comprises steps of forming a first LPD-SiO2 deposition preventing pattern on a semiconductor substrate(10), on which a desired layer is formed, to expose a portion of the desired layer, forming a first LPD-SiO2 layer(42) only on the exposed portion of the desired layer with a same height as the first LPD-SiO2 deposition preventing pattern, forming a second LPD-SiO2 deposition preventing pattern for covering an entire surface of the first LPD-SiO2 deposition preventing pattern and also exposing a portion of the first LPD-SiO2 layer, forming a second LPD-SiO2 layer(44) only on the exposed portion of the first LPD-SiO2 layer with a same height as the second LPD-SiO2 deposition preventing pattern, removing the first and second LPD-SiO2 deposition preventing pattern to remain only a dual damascene insulating layer for restraining a via hole and wire forming area on the desired layer, and filling the via hole and wire forming area with a conductive material to form a wire layer.

Abstract translation: 目的：使用LPD（液相沉积）硅氧烷层形成多层导线结构的方法是在使用双镶嵌工艺形成多层导线时使在金属线之间产生的寄生电容最小化。 构成：使用LPD（液相沉积）硅氧烷氧化物层形成多层线结构的方法包括以下步骤：在半导体衬底（10）上形成第一LPD-SiO 2沉积防止图案，在其上形成所需层 以露出所需层的一部分，仅在与第一LPD-SiO 2沉积防止图案相同的高度的所需层的暴露部分上形成第一LPD-SiO 2层（42），形成第二LPD-SiO 2沉积 防止图案覆盖第一LPD-SiO 2沉积防止图案的整个表面并且还暴露第一LPD-SiO 2层的一部分，仅在第一LPD-SiO 2层的暴露部分上形成第二LPD-SiO 2层（44） 层，其具有与第二LPD-SiO 2沉积防止图案相同的高度，去除第一和第二LPD-SiO 2沉积防止图案，以仅保留用于限制通孔和线形成区域的双镶嵌绝缘层 并且用导电材料填充通孔和线形成区域以形成线层。

公开(公告)号：KR100265759B1

公开(公告)日：2000-09-15

申请号：KR1019970049094

申请日：1997-09-26

Applicant: 삼성전자주식회사

Inventor： 구주선 ,  이해정 ,  김성호

IPC: H01L21/31

Abstract: PURPOSE: A method for fabricating a low-temperature interlayer dielectric using an electron beam is to cure a hydrogen silsesquioxane(HSQ) interlayer dielectric at a low temperature and simplify a manufacturing process of forming the HSQ interlayer dielectric. CONSTITUTION: The first insulating layer(104) is formed on a semiconductor substrate(100) with a substructure(102). An SOG(spin-on glass) layer(106) is coated on the first insulating layer. The second insulating layer(108) is formed on the SOG layer. The SOG layer is cured projecting an electron beam to the second insulating layer. The SOG layer is an HSQ. The substructure is a capacitor, whose dielectric layer is formed with one selected from the group consisting of ONO, Pb(Zr,Ti)O3, PbTiO3, (Pb,La)(Zr,Ti)O3, BaTiO3, (Ba,Sr)TiO3, Ta2O5 and SrTiO3. When the SOG layer is cured, a temperature of the semiconductor substrate is 20 deg.C to 500 deg.C.

Abstract translation: 目的：使用电子束制造低温层间电介质的方法是在低温下固化氢倍半硅氧烷（HSQ）层间电介质，并简化形成HSQ层间电介质的制造工艺。 构成：第一绝缘层（104）形成在具有子结构（102）的半导体衬底（100）上。 SOG（旋涂玻璃）层（106）被涂覆在第一绝缘层上。 第二绝缘层（108）形成在SOG层上。 固化SOG层将电子束投影到第二绝缘层。 SOG层是一个HSQ。 子结构是电容器，其电介质层由选自ONO，Pb（Zr，Ti）O 3，PbTiO 3，（Pb，La）（Zr，Ti）O 3，BaTiO 3，（Ba，Sr） TiO 3，Ta 2 O 5和SrTiO 3。 当SOG层固化时，半导体衬底的温度为20℃至500℃。

公开(公告)号：KR1020000033546A

公开(公告)日：2000-06-15

申请号：KR1019980050455

申请日：1998-11-24

Applicant: 삼성전자주식회사

Inventor： 구주선 ,  최지현 ,  이해정

IPC: H01L21/28

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent an area in which a damascene is not formed from damaging during the damascene forming process. CONSTITUTION: A semiconductor device comprises a substrate, a first material layer pattern,an etching prevention layer, a second material layer pattern, a mask layer pattern and conductive lines. The first material layer pattern is formed on the substrate, and has contact holes exposing predetermined areas of the substrate. The etching prevention layer is formed on the first material layer pattern. The second material layer pattern is formed on the etching prevention layer, and has windows exposing the contact holes and etching prevention layer pattern around the each contact hole. The mask layer pattern is formed on the second material layer pattern. The contact holes and windows are filled with the conductive lines.

Abstract translation: 目的：提供一种半导体器件及其制造方法，以防止在镶嵌过程中不形成镶嵌区域的损坏。 构成：半导体器件包括衬底，第一材料层图案，防蚀层，第二材料层图案，掩模层图案和导电线。 第一材料层图案形成在基板上，并且具有暴露基板的预定区域的接触孔。 防蚀层形成在第一材料层图案上。 第二材料层图案形成在防蚀层上，并且具有在每个接触孔周围露出接触孔和防蚀层图案的窗口。 掩模层图案形成在第二材料层图案上。 接触孔和窗口填充有导电线。

公开(公告)号：KR1019990062415A

公开(公告)日：1999-07-26

申请号：KR1019980020027

申请日：1998-05-30

Applicant: 삼성전자주식회사

Inventor： 정현담 ,  구주선

IPC: H01L21/3205

公开(公告)号：KR100207476B1

公开(公告)日：1999-07-15

申请号：KR1019960023690

申请日：1996-06-25

Applicant: 삼성전자주식회사

Inventor： 최지현 ,  황병근 ,  이해정 ,  구주선

IPC: H01L21/304

Abstract: 화학기계적 폴리싱에 의한 에치백 평탄화공정을 이용하는 반도체 장치의 제조 방법을 제공하는 것이다.
반동체 기판상에 도전물질을 증착한 다음 패터닝하여 도전층 패턴을 형성하는 단계; 도전층 패턴이 형성된 상기 결과물상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 SOG층을 형성하고 열처리하는 단계; 상기 SOG층상에 제2절연막을 형성하는 단계; 상기 결과물을 화학기계적 폴리싱 공정을 이용하여 에치백 평탄화하는 것을 특징으로하는 반도체 장치의 제조 방법을 제공하는 것이다.
상기 화학기계적 폴리싱 공정의 평탄화는 상기 도전층 패턴 위 부분의 SOG까지 제거하여 비어 콘택 부위에 SOG가 남지 않게 하는 것이 바람직하다.
따라서, 본 발명에 의한 화학기계적 폴리싱에 의한 에치백공정으로 종래 화학기계적 폴리싱 공정의 평탄화 방법에 따라 층간절연층을 평탄화시키는 경우 발생되는 디싱(dishing)현상을 방지할 수 있는 반도체 장치의 제조 방법을 얻게된다.

公开(公告)号：KR1019990048406A

公开(公告)日：1999-07-05

申请号：KR1019970067080

申请日：1997-12-09

Applicant: 삼성전자주식회사

Inventor： 구주선

IPC: H01L21/302

Abstract: 본 발명은 높은 단차가 형성된 반도체 기판에 제1 막 및 제2막을 침적하고, 단차가 낮은 영역의 제2막을 전자빔을 통하여 선택적으로 경화시킨 후, 습식식각을 진행함으로써 단차가 있는 반도체 기판에 형성된 층간절연막을 평탄화시킬 수 있는 방법에 관하여 개시한다. 전자빔에 의해 경화가 진행된 제2막, 예컨대 HSQ를 재질로 하는 SOG막은, 습식식각 과정에서 경화가 진행되지 않은 막질에 비하여 현저하게 식각율이 낮아지기 때문에 층간절연막에 대한 용이한 평탄화를 수행할 수 있다.