中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

37 records (took 0.026 seconds)

    적층 칩 패키지 및 그 제조 방법
    33.
    发明公开
    적층 칩 패키지 및 그 제조 방법 有权
    堆叠芯片包装及其形成方法

    公开(公告)号：KR1020080036444A

    公开(公告)日：2008-04-28

    申请号：KR1020060103043

    申请日：2006-10-23

    Applicant: 삼성전자주식회사

    Inventor： 정세영 ,  김남석 ,  조차제 ,  이종호 ,  박명순

    IPC: H01L23/12

    CPC classification number: H01L23/3114 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2225/06524 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

    Abstract: A stacked chip package and a method for manufacturing the same are provided to prevent reliability degradation due to the curve and protrusion of a bonding wire by using a metal wire for electrically connecting first and second semiconductor chip instead of a bonding wire. A second semiconductor chip(30) is laminated on a first semiconductor chip(10). A spacer(20a) is formed at a side of the semiconductor chip. A metal wire(65) is formed on the spacer to electrically connect the first semiconductor chip to the second semiconductor chip. The spacer is formed by using an adhesive agent. When the metal wire is formed, a wire layer for the metal wire is formed and the wire layer is patterned. When the wire layer is formed, a seed metal layer is formed. A metal layer is formed on the seed metal layer by an electroplating process. The metal wire is copper. The copper metal wire is formed by an electroplating method. A solder bump is formed on the metal wire.

    Abstract translation: 提供堆叠式芯片封装及其制造方法，以通过使用用于电连接第一和第二半导体芯片而不是接合线的金属线来防止由于接合线的弯曲和突出引起的可靠性劣化。 第二半导体芯片（30）层叠在第一半导体芯片（10）上。 在半导体芯片的一侧形成间隔物（20a）。 在间隔物上形成金属线（65），以将第一半导体芯片电连接到第二半导体芯片。 间隔物通过使用粘合剂形成。 当形成金属线时，形成用于金属线的金属丝层，并对金属丝图案进行图案化。 当形成导线层时，形成种子金属层。 通过电镀工艺在种子金属层上形成金属层。 金属线是铜。 铜金属线由电镀法形成。 在金属丝上形成焊料凸块。

    금속기저층의 언더컷 보상 방법 및 그를 이용한 웨이퍼레벨 칩 스케일 패키지 제조 방법
    35.
    发明授权
    금속기저층의 언더컷 보상 방법 및 그를 이용한 웨이퍼레벨 칩 스케일 패키지 제조 방법 失效
    금속기저층의언더컷보상방법및그를이용한웨이퍼레벨칩스케일패키지제조방

    公开(公告)号：KR100639703B1

    公开(公告)日：2006-10-30

    申请号：KR1020050072883

    申请日：2005-08-09

    Applicant: 삼성전자주식회사

    Inventor： 박명순 ,  유승관 ,  심성민 ,  장동현 ,  정현수 ,  이인영 ,  정재식 ,  김순범 ,  최주일

    IPC: H01L23/48 ,  H01L21/60

    Abstract: A method for compensating for an undercut of a metal base layer is provided to guarantee the area of a metal base layer by compensating for an undercut of a metal base layer under a redistribution layer or a solder bump. An insulation layer is formed on a semiconductor wafer(91). The insulation layer is covered with a multilayered metal base layer(92). A photomask having an open part is formed on the metal base layer(93). The photomask is dry-etched to form a concave part that rounds toward the inner lower part of the inner wall of the open part adjacent to the metal base layer(94). The open part including the concave part is filled with a plating layer(95). The photomask is eliminated(96). The metal base layer outside the plating layer is wet-etched(97). The metal base layer that is etched toward the inside of the outer surface of the plating layer on the upper part of a protrusion part is reduced by the protrusion part of the plating layer filled in the concave part so that an area of the metal base layer under the plating layer is guaranteed. The plating layer can be a redistribution layer or a solder plating layer for a solder bump.

    Abstract translation: 提供一种用于补偿金属基层的底切的方法，以通过补偿重新分布层或焊料凸块下方的金属基层的底切来保证金属基层的面积。 在半导体晶片（91）上形成绝缘层。 绝缘层覆盖有多层金属基层（92）。 在金属基底层（93）上形成具有开口部分的光掩模。 对光掩模进行干蚀刻，形成朝向与金属基底层（94）邻接的开口部的内壁的内侧下部呈圆形的凹部。 包括凹部的开口部分填充有镀层（95）。 光罩被消除（96）。 对电镀层外部的金属基层进行湿蚀刻（97）。 通过填充在凹部中的镀层的突出部分来减少在突出部分的上部上朝向镀层的外表面内侧蚀刻的金属基底层，从而使金属基底层的面积 在镀层下有保证。 镀层可以是用于焊料凸块的再分布层或焊料镀层。

Patent Agency Ranking