-
公开(公告)号：KR1020090006627A
公开(公告)日：2009-01-15
申请号：KR1020070070152
申请日：2007-07-12
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/792 , H01L21/28282 , H01L29/42348 , H01L29/513 , H01L29/66833 , H01L21/265
Abstract: A nonvolatile memory device and a manufacturing method thereof are provided to increase threshold voltage window and to steadily maintain supply voltage in removing by forming a tunnel insulation film of multi layer structure. A tunnel insulation film(130) is formed on a semiconductor substrate(100). An electric charge storing film(140) is formed on the tunnel insulation film. A blocking insulation film(150) is formed on the electric charge storing film. A control gate electrode(160) is formed on the blocking insulation film. The tunnel insulation film includes a first tunnel insulation film(110) and a second tunnel insulation film(120).
Abstract translation: 提供非易失性存储器件及其制造方法以增加阈值电压窗口并通过形成多层结构的隧道绝缘膜来稳定地维持去除中的电源电压。 隧道绝缘膜（130）形成在半导体衬底（100）上。 在隧道绝缘膜上形成电荷存储膜（140）。 在电荷存储膜上形成阻挡绝缘膜（150）。 在阻挡绝缘膜上形成控制栅电极（160）。 隧道绝缘膜包括第一隧道绝缘膜（110）和第二隧道绝缘膜（120）。
-
公开(公告)号：KR1020070062337A
公开(公告)日：2007-06-15
申请号：KR1020050122157
申请日：2005-12-12
Applicant: 삼성전자주식회사
CPC classification number: H01L21/76877 , B82Y40/00 , H01L21/02527 , H01L21/02606 , H01L21/7684
Abstract: A method for forming a carbon nano tube of a semiconductor device and a related device are provided to enhance gap fill characteristics and to reduce resistance of a metal line. A carbon nano tube is provided(110). A shortened carbon nano tube is formed by performing a predetermined treatment on the carbon nano tube(120). A complex metal line material is formed by mixing an additive to the shortened carbon nano tube(130). A conductive layer is formed on the substrate by using the complex metal line material(140). A metal line is formed by removing partially the conductive layer therefrom(150).
Abstract translation: 提供一种用于形成半导体器件的碳纳米管和相关器件的方法，以增强间隙填充特性并降低金属线的电阻。 提供碳纳米管（110）。 通过在碳纳米管（120）上进行预定处理来形成缩短的碳纳米管。 通过将添加剂与缩短的碳纳米管（130）混合形成复合金属线材料。 通过使用复合金属线材料（140）在基板上形成导电层。 通过从其上部分地去除导电层而形成金属线（150）。
-
公开(公告)号：KR100725172B1
公开(公告)日：2007-06-04
申请号：KR1020060005532
申请日：2006-01-18
Applicant: 삼성전자주식회사
IPC: H01L27/115 , B82Y10/00
Abstract: 다치형 비휘발성 기억 장치를 제공한다. 이 비휘발성 기억 장치는 소오스 영역 및 드레인 영역 사이에 정의된 채널 영역과, 상기 채널 영역 상부에 위치하고 전하가 저장되는 전하저장층과, 상기 채널 영역 및 상기 전하저장층 사이에 개재되어 전하가 터널링되는 터널절연막을 구비한다. 터널절연막에는 양자 제한 효과를 나타내는 양자 제한막을 포함함으로써 기입 전압에 따라 터널링 전류가 계단형으로 증가하여 데이터 비트 사이의 문턱 전압 간격이 크고, 문턱 전압의 산포가 낮은 특성을 나타낸다.
멀티비트, 다치형, 비휘발성, 소노스-
公开(公告)号：KR1020060118898A
公开(公告)日：2006-11-24
申请号：KR1020050041331
申请日：2005-05-17
Applicant: 삼성전자주식회사
IPC: H01L27/10 , H01L27/108
CPC classification number: H01L29/42328 , H01L29/42336 , H01L29/66825 , H01L29/7881
Abstract: A semiconductor memory device and a manufacturing method thereof are provided to improve short channel effect of a sensing transistor by arranging a control gate line for controlling the sensing transistor. A body layer pattern(22) is located on a substrate(20). A source region(24) and a drain region(26) are located in the body layer pattern to be separated from each other. A data line(30) crosses an upper portion of a channel region(28) between the source region and the drain region. An MTJ(Multiple Tunnel Junction) barrier layer(32) is arranged between the gate line and the channel line. A floated storage node(34) is located between the channel region and the MTJ barrier layer. A first control gate line(38) crosses an upper portion of the data line and covers both sidewalls of the storage node and both sidewalls of the MTJ barrier layer. A second control gate line(42) is located on a lower portion of the channel region and crosses a lower portion of the body layer pattern.
Abstract translation: 提供一种半导体存储器件及其制造方法，用于通过布置用于控制感测晶体管的控制栅极线来改善感测晶体管的短沟道效应。 体层图案（22）位于基底（20）上。 源区域（24）和漏极区域（26）位于体层图案中以彼此分离。 数据线（30）与源极区域和漏极区域之间的沟道区域（28）的上部相交。 栅极线和通道线之间布置有MTJ（多隧道结）阻挡层（32）。 浮动存储节点（34）位于通道区域和MTJ阻挡层之间。 第一控制栅极线（38）跨越数据线的上部并且覆盖存储节点的两个侧壁和MTJ阻挡层的两个侧壁。 第二控制栅极线（42）位于沟道区的下部并与本体层图案的下部交叉。
-
公开(公告)号：KR1020060114991A
公开(公告)日：2006-11-08
申请号：KR1020050037244
申请日：2005-05-03
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L29/78
CPC classification number: H01L27/108 , H01L21/84 , H01L27/10802 , H01L27/1203 , H01L29/7841 , H01L27/10882
Abstract: Single transistor floating body DRAM devices having a vertical channel transistor structure and manufacturing methods thereof are provided to increase integration by using a gate electrode vertically arranged between floating bodies. A pair of first and second floating bodies(25,35) are located on a semiconductor substrate(10) to be separated from each other. A source region(37) and drain regions(27,28) are located in a lower portion of an upper portion of the first and the second floating bodies. A gate electrode is arranged between the first and the second floating bodies. The gate electrode includes first and second gate electrodes(40a,40b). The first gate electrode covers a sidewall of the first floating body. The second gate electrode covers a sidewall of the second floating body. A bit line(51) is arranged on the first and the second floating bodies and electrically connected to the drain regions.
Abstract translation: 提供具有垂直沟道晶体管结构的单晶体管浮体DRAM器件及其制造方法，以通过使用垂直布置在浮体之间的栅电极来增加集成度。 一对第一和第二浮体（25,35）位于半导体衬底（10）上以彼此分离。 源极区域（37）和漏极区域（27,28）位于第一和第二浮体的上部的下部。 栅电极设置在第一和第二浮体之间。 栅电极包括第一和第二栅电极（40a，40b）。 第一栅电极覆盖第一浮体的侧壁。 第二栅极电极覆盖第二浮体的侧壁。 位线（51）布置在第一和第二浮体上并电连接到漏区。
-
Patent Agency Ranking
公开(公告)号：KR100560657B1
公开(公告)日：2006-03-16
申请号：KR1020030008797
申请日：2003-02-12
Applicant: 삼성전자주식회사
Inventor： 백승재
IPC: G11C5/02
Abstract: 상변환 기억소자의 셀 어레이 및 그 동작 방법을 제공한다. 이 기억소자의 어레이는, 반도체 기판에 매트릭스상으로 배열된 복수개의 기억소자들로 구성된다. 각 기억소자는 각각 억세스 트랜지스터 및 가변저항체로 구성된다. 각 행의 일 단에 선택 트랜지스터가 배치된다. 각 행의 억세스 트랜지스터들의 게이트 전극들 및 선택 트랜지스터의 게이트 전극은 워드라인에 병렬로 접속된다. 각 열의 가변저항체는 비트라인에 병렬로 접속된다. 각 행의 억세스 트랜지스터들의 소오스 영역들은 동일행의 선택 트랜지스터의 드레인에 병렬로 접속된다.
-
公开(公告)号：KR101663566B1
公开(公告)日：2016-10-07
申请号：KR1020100018882
申请日：2010-03-03
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582
Abstract: 3차원반도체기억소자및 그형성방법을제공한다. 이소자에따르면, 활성구조체는적층된제1 게이트들의측벽들과중첩된제1 수직형활성부및 적층된제2 게이트들의측벽들과중첩된제2 수직형활성부를포함한다. 기판내에접속도핑된영역이형성된다. 접속도핑된영역은제1 및제2 수직형활성부들의하단들과연결된다. 제1 게이트들은적층된복수의제1 셀게이트들및 최상위의제1 셀게이트상부에배치된스트링선택게이트를포함하고, 제2 게이트들은적층된복수의제2 셀게이트들및 최상위의제2 셀게이트상부에배치된접지선택게이트를포함한다.
-
公开(公告)号：KR1020110068590A
公开(公告)日：2011-06-22
申请号：KR1020090125618
申请日：2009-12-16
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: G11C16/0483 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/66666 , H01L29/7827 , H01L29/7926 , H01L27/0688
Abstract: PURPOSE: A semiconductor device and manufacturing method thereof are provided to reduce trap density, thereby enhancing the threshold voltage distribution of a cell memory transistor. CONSTITUTION: A plurality of gate patterns(25g,25w,25s) is laminated on a semiconductor layer. Gate interlayer insulation patterns are arranged between the gate patterns. Active posts(9a) penetrate the gate patterns and the gate interlayer insulation patterns and contact a semiconductor layer. A gate insulating film is interposed between the active posts and the gate patterns. The active posts include one side of the active posts contacting the gate insulating film and the gate interlayer insulation patterns. One side of the active posts has an uneven structure.
Abstract translation: 目的：提供半导体器件及其制造方法以减小陷阱密度，从而提高单元存储晶体管的阈值电压分布。 构成：在半导体层上层叠多个栅极图案（25g，25w，25s）。 栅极层间绝缘图案布置在栅极图案之间。 活性柱（9a）穿透栅极图案和栅极层间绝缘图案并接触半导体层。 栅极绝缘膜介于活性柱和栅极图案之间。 活性柱包括接触栅极绝缘膜的活性柱和栅极层间绝缘图案的一侧。 活动岗位的一侧具有不均匀的结构。
-
公开(公告)号：KR1020110068145A
公开(公告)日：2011-06-22
申请号：KR1020090124990
申请日：2009-12-15
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/28 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L21/76205
Abstract: PURPOSE: A method for manufacturing a rewriteable three dimensional memory device is provided to reduce interface trap density by processing the rear side of the semiconductor film by surface treatment to form an oxidation passivation film. CONSTITUTION: In a method for manufacturing a rewriteable three dimensional memory device, a thin film structure is formed on a substrate(S10). A penetration area exposing a substrate to outside is formed by patterning the thin film structure(S20). A semiconductor film is uniformly formed on the inner side of a penetration region(S30). An oxidation passivation film is formed on the surface of the exposed semiconductor film to the penetration region by processing the semiconductor film through surface treatment(S40). An insulating layer filling the penetration region is formed after processing the semiconductor film by surface treatment.
Abstract translation: 目的：提供一种用于制造可重写三维存储器件的方法，通过表面处理来处理半导体膜的后侧以形成氧化钝化膜来减少界面陷阱密度。 构成：在可重写三维存储器件的制造方法中，在衬底上形成薄膜结构（S10）。 通过对薄膜结构进行构图来形成将衬底暴露于外部的穿透区域（S20）。 半导体膜均匀地形成在穿透区域的内侧（S30）。 通过表面处理处理半导体膜，在暴露的半导体膜的表面上形成氧化钝化膜到穿透区域（S40）。 在通过表面处理处理半导体膜之后形成填充穿透区域的绝缘层。
-
公开(公告)号：KR1020100028917A
公开(公告)日：2010-03-15
申请号：KR1020080087868
申请日：2008-09-05
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L21/28282 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L21/28185
Abstract: PURPOSE: A non-volatile memory device and a methods of forming the same are provided to easily control a element content ratio of a multi-element insulating layer by supplying a first, a second, and a third source successively. CONSTITUTION: A tunnel insulating layer is formed on a substrate. An insulating film with plurality of elements is formed by supplying a first, a second, a third source in order. A charge storage layer is formed on a tunnel insulating layer. A blocking insulating layer is formed on the charge storage layer. A control gate electrode is formed on the blocking insulation film.
Abstract translation: 目的：提供一种非易失性存储器件及其形成方法，以通过依次提供第一，第二和第三源来容易地控制多元件绝缘层的元件含量比。 构成：在基板上形成隧道绝缘层。 通过依次提供第一，第二，第三源，形成具有多个元件的绝缘膜。 在隧道绝缘层上形成电荷存储层。 在电荷存储层上形成阻挡绝缘层。 在阻挡绝缘膜上形成控制栅电极。
-
-
-
-
-
-
-
-
-
Search Results
63
records
(took 0.026 seconds)
