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公开(公告)号：KR1020070016276A
公开(公告)日：2007-02-08
申请号：KR1020050070651
申请日：2005-08-02
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76877 , H01L21/31144 , H01L21/76802 , H01L21/76831
Abstract: 라인 타입 패턴 형성 방법에 있어서, 기판 상에 제1방향으로 연장되고 제1간격을 갖는 평행한 직선들 상에 각각 배치된 콘택 영역들을 번갈아 노출시키는 제1개구부를 갖는 층간 절연막 패턴을 형성한다. 제1개구부를 매립하는 콘택 플러그들을 형성한다. 콘택 플러그들과 연결되고, 콘택 플러그들 사이의 층간 절연막 패턴 부분들을 노출시키면서 제1방향과 실질적으로 수직하는 제2방향으로 연장되며, 제1간격보다 넓은 제2간격으로 제1도전 패턴들을 형성한다. 층간 절연막 패턴을 부분적으로 식각함으로써 제1도전 패턴들 사이의 콘택 영역을 노출시키는 제2개구부를 형성한다. 제2개구부 내부에 매립되며 제1도전 패턴의 단면과 실질적으로 동일한 단면적을 가지면서 제2방향으로 연장되는 제2도전 패턴을 형성한다. 상기한 방법에 의하면, 미세한 간격을 갖는 라인 형상의 도전 패턴을 브릿지(bridge) 또는 낫칭(notching)이 없이 형성할 수 있다.
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公开(公告)号：KR1020070015778A
公开(公告)日：2007-02-06
申请号：KR1020050070355
申请日：2005-08-01
Applicant: 삼성전자주식회사
IPC: H01L21/8242
Abstract: 디램 반도체 장치의 형성방법에 관한 것이다. 먼저 제2 층간 절연막 상에 하부의 제1 콘택 패드와 이웃하는 제2 방향으로 연장되고, 제1 폭을 갖는 제1 라인 및 상기 제1 라인과 연결되고, 상기 제1 폭에 비해 넓은 제2 폭을 갖는 제2 라인을 포함하는 금속배선을 형성한다. 이어서 상기 금속배선 사이를 충분하게 매립시키는 제3 층간 절연막 패턴을 형성한다. 계속하여 상기 금속배선을 식각마스크로 이용한 전면 식각을 수행하여 상기 제3 층간 절연막 패턴 및 제2 층간 절연막 패턴의 일부를 제거함으로써 상기 제1 콘택 패드를 노출시킨다. 이로써, 식각 레지듀(residue)의 제거가 잘되고 낫 오픈(not-open) 현상이 감소된다.
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公开(公告)号：KR1020060134240A
公开(公告)日：2006-12-28
申请号：KR1020050053768
申请日：2005-06-22
Applicant: 삼성전자주식회사
IPC: H01L21/82
CPC classification number: H01L27/101 , H01L23/5258 , H01L2924/0002 , H01L2924/00
Abstract: A fuse of a semiconductor device and its forming method are provided to prevent the cutting of the fuse itself and to obtain uniform fuses by performing an etching process on interlayer dielectrics using an etch stop layer with a relatively different etch selectively compared to the interlayer dielectrics. A semiconductor substrate(100) includes a memory cell region and a fuse box region. A first interlayer dielectric(106) is formed on the substrate. A first etch stop layer(108) is formed on the first interlayer dielectric. A metal line(122a) is formed on the first etch stop layer of the memory cell region. The metal line is composed of a barrier layer, a metal film and a capping layer. A plurality of fuses(122b) are formed on the first etch stop layer of the fuse box region. A second interlayer dielectric is formed on the metal line and the first etch stop layer. The second interlayer dielectric has an opening portion for exposing the fuse box region to the outside.
Abstract translation: 提供了半导体器件的熔断器及其形成方法，以防止熔丝本身的切割并且通过使用具有相对不同蚀刻的蚀刻停止层对层间电介质进行蚀刻处理来获得均匀的熔丝，与蚀刻停止层相比，与层间电介质相比选择性相对较差。 半导体衬底（100）包括存储单元区域和保险丝盒区域。 在基板上形成第一层间电介质（106）。 第一蚀刻停止层（108）形成在第一层间电介质上。 金属线（122a）形成在存储单元区域的第一蚀刻停止层上。 金属线由阻挡层，金属膜和覆盖层构成。 多个保险丝（122b）形成在保险丝盒区域的第一蚀刻停止层上。 在金属线和第一蚀刻停止层上形成第二层间电介质。 第二层间电介质具有用于将保险丝盒区域暴露于外部的开口部分。
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公开(公告)号：KR1020010028674A
公开(公告)日：2001-04-06
申请号：KR1019990041055
申请日：1999-09-22
Applicant: 삼성전자주식회사
IPC: H01L27/06
Abstract: PURPOSE: A method for manufacturing a hole of a semiconductor device having high selectivity using reactive ion etching is provided to prevent undesired etching during an etching process for forming a self-aligned contact hole, by using C4F8 gas as etching gas in a reactive ion etching chamber to obtain high selectivity. CONSTITUTION: A conductive layer pattern having an upper surface and a side surface is formed on a semiconductor substrate(100). A cap layer(133,143) composed of the first insulating material is formed on the conductive layer pattern. A spacer(151,152,161,162) composed of the first insulating material is formed on a side surface of the conductive layer pattern and the cap layer. An insulating layer composed of the second insulating material is formed on the semiconductor substrate to cover the cap layer and the spacer. A mask layer pattern is formed on the insulating layer. The insulating layer is etched in a reactive ion etching chamber by using the mask layer pattern as an etching mask, wherein C4F8 gas of 10-20 sccm is used as etching gas and carbon monoxide gas not greater than 400 sccm and inert gas of 200-600 sccm are used as additive gas. Oxygen gas not greater than 10 sccm is supplied into the chamber. Pressure of the chamber is 20-60 milli torr, and radio frequency power applied to the chamber is 1000-2000 watts. The temperature of the chamber is 0-60 deg.C.
Abstract translation: 目的：提供一种使用反应离子蚀刻制造具有高选择性的半导体器件的孔的方法，以在用于形成自对准接触孔的蚀刻工艺期间通过在反应离子蚀刻中使用C 4 F 8气体作为蚀刻气体来防止不希望的蚀刻 室以获得高选择性。 构成：在半导体衬底（100）上形成具有上表面和侧表面的导电层图案。 由导电层图案形成由第一绝缘材料构成的覆盖层（133,143）。 在导电层图案和盖层的侧表面上形成由第一绝缘材料构成的间隔物（151,152,161,162）。 在半导体衬底上形成由第二绝缘材料构成的绝缘层，以覆盖覆盖层和间隔物。 在绝缘层上形成掩模层图案。 通过使用掩模层图案作为蚀刻掩模，在反应离子蚀刻室中蚀刻绝缘层，其中使用10-20sccm的C 4 F 8气体作为蚀刻气体，不大于400sccm的一氧化碳气体和200sccm的惰性气体， 600sccm用作添加气体。 不大于10sccm的氧气被供应到室中。 室的压力为20-60毫乇，施加到室的射频功率为1000-2000瓦。 室内温度为0-60摄氏度。
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公开(公告)号：KR1019940004994B1
公开(公告)日：1994-06-09
申请号：KR1019910008757
申请日：1991-05-28
Applicant: 삼성전자주식회사
IPC: H01L21/70
Abstract: forming a first and second conductive layer on a contact hole, to fill the contact hole; carrying out a first etch back process until a native oxide formed at the interface between the first and second conductive layer is exposed; carrying out a second etch back process under the condition that first conductive layer and the native oxide have the same etch rate, to leave first and second conductive layer only in the contact hole; forming a third conductive layer on the substrate or conductive layer, thereby reducing the contact resistance and improving the step coverage of the metal layer.
Abstract translation: 在接触孔上形成第一和第二导电层，以填充接触孔; 执行第一回蚀工艺，直到在第一和第二导电层之间的界面处形成的自然氧化物暴露; 在第一导电层和天然氧化物具有相同的蚀刻速率的条件下进行第二次回蚀工艺，仅将第一和第二导电层留在接触孔中; 在基板或导电层上形成第三导电层，从而降低接触电阻并改善金属层的台阶覆盖。
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Patent Agency Ranking
公开(公告)号：KR1019940001407A
公开(公告)日：1994-01-20
申请号：KR1019920011025
申请日：1992-06-24
Applicant: 삼성전자주식회사
IPC: H01L27/108
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公开(公告)号：KR1019930001335A
公开(公告)日：1993-01-16
申请号：KR1019910010685
申请日：1991-06-26
Applicant: 삼성전자주식회사
IPC: H01L21/306
Abstract: 내용 없음
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公开(公告)号：KR1020070113778A
公开(公告)日：2007-11-29
申请号：KR1020060047506
申请日：2006-05-26
Applicant: 삼성전자주식회사
IPC: H01L21/306
CPC classification number: H01L21/67069 , G03F7/2028
Abstract: An apparatus for etching the edge of a wafer is provided to prevent a wafer and a stage from being attached to each other by static electricity and so forth by reducing the contact area between the wafer and the stage. An etching gas supply part supplies an etching gas to the inside of a process chamber(110). A wafer stage(120) includes a stage body(122) disposed in the chamber and a plurality of support members with a pin shape formed on the upper surface of the stage body. The support members support the wafer while the wafer is separated from the stage body. From the etching gas, a shield part(150) shields the center part of the wafer supported on the wafer stage except the edge of the wafer. RF power is applied to a lower electrode(140) disposed along the circumference of the wafer stage. An upper electrode(160) is disposed on the chamber to confront the lower electrode. Lift pins(144) penetrate the stage and transfer vertically so that the wafer is moved up/down with respect to the stage.
Abstract translation: 提供一种用于蚀刻晶片边缘的装置，以通过减小晶片和台架之间的接触面积来防止晶片和平台通过静电等彼此附接。 蚀刻气体供给部将蚀刻气体供给到处理室（110）的内部。 晶片台（120）包括设置在腔室中的台体（122）和形成在台体上表面上的销形状的多个支撑构件。 支撑构件在晶片与载物台分离的同时支撑晶片。 从蚀刻气体中，屏蔽部分（150）屏蔽除晶片边缘外的晶片载台上的晶片的中心部分。 RF功率被施加到沿着晶片台的圆周设置的下电极（140）。 上电极（160）设置在腔室上以面对下电极。 提升销（144）穿透平台并垂直移动，使晶片相对于平台上下移动。
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公开(公告)号：KR1020070111175A
公开(公告)日：2007-11-21
申请号：KR1020060044214
申请日：2006-05-17
Applicant: 삼성전자주식회사
IPC: H01L21/3063 , H01L21/336 , H01L21/28 , H01L21/3065
CPC classification number: H01L21/76802 , H01L21/31111 , H01L29/66477
Abstract: A method for forming a pattern is provided to prevent a semiconductor substrate from being damaged by a conventional anisotropic etch process by partially damaging a silicon nitride layer by non-volatile gas and by removing the damaged silicon nitride by a solution for etching an oxide. A silicon nitride layer is formed on a substrate(100). A part of the silicon nitride layer is damaged by a plasma treatment using an inert gas. The inert gas can include He, Ar, Kr or Xe. The damaged part of the silicon nitride layer is selectively eliminated to expose the upper surface of the substrate by a wet etch process using a solution for etching an oxide. The solution for etching the oxide can include HF.
Abstract translation: 提供了形成图案的方法，以防止通过常规的各向异性蚀刻工艺损坏半导体衬底，通过非挥发性气体部分损坏氮化硅层和通过用于蚀刻氧化物的溶液去除损坏的氮化硅。 在衬底（100）上形成氮化硅层。 氮化硅层的一部分通过使用惰性气体的等离子体处理而损坏。 惰性气体可包括He，Ar，Kr或Xe。 通过使用蚀刻氧化物的溶液的湿式蚀刻工艺选择性地去除氮化硅层的损坏部分以暴露衬底的上表面。 用于蚀刻氧化物的溶液可以包括HF。
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